Manufacture of face-down microelectronic packages

A method, comprising:

• (a) attaching a first major surface of a first microelectronic element to a first surface of a substrate such that a plurality of contacts at the first major surface of the first microelectronic element are aligned with a first opening extending through the substrate;
• (b) attaching a second microelectronic element atop a second major surface of the first microelectronic element, the second major surface opposite the first major surface, such that a plurality of contacts at a surface of the second microelectronic element facing the substrate are disposed beyond an edge of the first microelectronic element and are aligned with a second opening in the substrate other than the first opening;
• (c) assembling a third microelectronic element and a fourth microelectronic element with the first and second microelectronic elements to respective positions overlying the surface of the substrate such that the first and third microelectronic elements are each adjacent to the major surface of the substrate and are spaced apart from one another, and each of the second and fourth microelectronic elements partially overlies the first and third microelectronic elements and has contacts exposed beyond edges of the first and third microelectronic elements, and
• (c) forming electrical connections between the first microelectronic element and the substrate, between the second microelectronic element and the substrate, between the third microelectronic element and the substrate and between the fourth microelectronic element and the substrate,
• wherein steps (a), (b), and (c) include transferring the first, second, third, and fourth microelectronic elements from first, second, third, and fourth positions of a single diced wafer to respective positions overlying the first surface of the substrate, wherein the positions of the diced wafer are selected so as to maximize compound speed bin yield of the microelectronic package when performing steps (a), (b) and (c) in high volume manufacturing.

A method of manufacturing a microelectronic package, comprising:

• (a) adhesively attaching major surfaces of first, second, third and fourth microelectronic elements to a major surface of a first substrate, such that each of the microelectronic elements is spaced apart from all others of the first, second, third and fourth microelectronic elements in at least one direction parallel to the major surface,
• wherein step (a) includes transferring the first, second, third and fourth microelectronic elements from original positions of a single wafer;
• and
• (b) after step (a), forming electrical connections between the first, second, third and fourth microelectronic elements and the first substrate;
• wherein steps (a) and (b) include transferring the microelectronic elements from positions of a single diced wafer to respective attachment positions of the major surface of the substrate, wherein the positions of the diced wafer are selected so as to maximize compound speed bin yield of the microelectronic package when performing steps (a) and (b) in high volume manufacturing.