Wafer warpage reduction
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun Hsiung Tsai, Shiang-Rung Tsai
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun Hsiung Tsai, Shiang-Rung Tsai
Estimating the term…
The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed.
A method of layer deposition on a substrate, comprising:
A method of epitaxial layer deposition on a substrate, comprising:
A method, comprising:
Dependencies are inferred from the claim text.