High productivity combinatorial workflow for post gate etch clean development
AssigneeIntermolecular, Inc.
InventorJohn Foster
Life of this patent
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Abstract
Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.
Claims20
A method, comprising:
- forming a dielectric layer on a substrate;
- forming a plurality of metal gate stacks over the dielectric layer;
- defining site isolated regions on the substrate, wherein each site isolated region comprises at least one of the metal gate stacks;
- applying liquid chemicals to each of the site isolated regions, wherein at least one of the composition or the application condition of the liquid chemicals is varied in a combinatorial manner between the site isolated regions;
- and
- measuring a structural characteristic of a metal-containing layer in the metal gate stacks;
- wherein the liquid chemicals remove a contaminant from at least one of the metal gate stacks.
A method for screening post gate etch clean processes in a combinatorial manner, the method comprising:
- forming a dielectric layer on a substrate;
- defining two or more site isolated regions on the dielectric layer;
- forming at least one metal gate stack in each site isolated region;
- applying liquid chemicals to each of the site isolated regions, wherein at least one of the composition or the application condition of the liquid chemicals is varied in a combinatorial manner between the site isolated regions, and the liquid chemicals selectively etch a contaminant from the at least one metal gate stack in at least one of the site-isolated regions;
- rinsing the substrate after the liquid chemicals are applied;
- and
- measuring a structural characteristic of a metal-containing layer in the metal gate stacks within each site isolated region.
A method for screening post gate etch clean processes in a combinatorial manner, the method comprising:
- defining two or more site isolated regions on a substrate;
- forming a dielectric layer in each site isolated region;
- forming at least one metal gate stack in each site isolated region;
- applying liquid chemicals to each of the site isolated regions;
- and
- measuring a structural characteristic of the metal-containing layer in the metal gate stacks within each site isolated region;
- wherein the liquid chemicals selectively etch a contaminant from, and form an undercut feature in, the at least one metal gate stack of at least one of the site-isolated regions;
- and
- wherein at least one of the material or the process condition of the forming of the dielectric layer is varied in a combinatorial manner between the site isolated regions.
Dependencies are inferred from the claim text.