Process for producing chip

A process for producing a chip in which plural ejection orifice arrays are arranged, the process comprising the steps of:

• conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed on the substrate while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the photosensitive resin layer,
• developing the ejection orifice array patterns to form ejection orifice arrays in the photosensitive resin layer, and
• dividing the wafer having the photosensitive resin layer in which the ejection orifice arrays have been formed to form plural chips in which the plural ejection orifice arrays are arranged,
• wherein the reduction projection exposure is conducted once to form in the photosensitive resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction of ejection orifice arrays in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in another one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction of ejection orifice arrays in a further one chip.