Packet assembly module for multi-core, multi-thread network processors
OwnerDeepak Mital, James Clee +1inventors
InventorsDeepak Mital, James Clee, Jerry Pirog
Life of this patent
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OwnerDeepak Mital, James Clee +1inventors
InventorsDeepak Mital, James Clee, Jerry Pirog
Estimating the term…
Described embodiments provide a packet assembler for a network processor. The network processor includes a plurality of processing modules for processing received packets into one or more processed-packet portions. A shared system memory of the network processor receives processed-packet portions corresponding to packet assemblies. Each of the packet assemblies has associated tasks. A packet assembly processor constructs an output packet for each packet assembly from the processed-packet portions in accordance with instructions from the tasks associated with the packet assembly. The packet assembly processor coordinates storage of the processed-packet portions for each output packet that is read from the system memory based on the instructions from the tasks associated with the corresponding packet assembly.
A packet assembler for a network processor implemented as a system-on-chip, the network processor processing received packets with a plurality of processing modules into one or more processed-packet portions, the network processor coupled to an external memory, the packet assembler comprising:
A method of assembling output packets of a network processor implemented as a system-on-chip, the network processor processing received packets with a plurality of processing modules into one or more processed-packet portions, the network processor coupled to an external memory, the method comprising:
A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of assembling output packets of a network processor implemented as a system-on-chip, the network processor processing received packets with a plurality of processing modules into one or more processed-packet portions, the network processor coupled to an external memory, the method comprising:
Dependencies are inferred from the claim text.