Simulating scan tests with reduced resources

A non-transitory machine readable medium storing one or more sequences of instructions for causing a system to facilitate the design of an integrate circuit, wherein execution of said one or more sequences of instructions by one or more processors contained in said system causes said system to perform the actions of:

• receiving a design data representing said IC at a logic level, said integrated circuit containing a plurality of memory elements and a plurality of combination logics which together provide an intended utility of said IC in a functional mode, said plurality of memory elements further being configurable to form a set of scan chains in a test mode;
• identifying a set of memory elements which are present in said set of scan chains, wherein each of said set of memory elements has a same data output connected to a next element in a corresponding scan chain and also a corresponding combinational logic according to said design data;
• replacing each of said set of memory elements with a corresponding one of a set of a new elements, wherein a single data output path of at least one memory element is replaced with two paths, with each path being operable in a corresponding one of a shift phase and a capture phase, wherein each new element has two paths to provide the corresponding data output, with one path being operable to connect the data value to the combinational logic only during a capture phase of said test mode, and the second path being operable to connect the data value to the next element in the chain during a shift phase of said test mode;
• and
• simulating a plurality of scan tests on said IC with said set of new elements.

A digital processing system comprising:

• a memory to store a first library and a second library, said first library containing a plurality of types of memory elements and said second library containing a new element for each of said plurality of types of memory elements,
• wherein each of said set of plurality of types of memory elements has a single data output, wherein a single data output path of at least one memory element is replaced with two paths, with each path being operable in a corresponding one of a shift phase and a capture phase,
• wherein each new element has two paths to provide the corresponding data output, with one path being operable to connect the data value only during a capture phase of a test mode, and the second path being operable to connect the data value during a shift phase of said test mode;
• and
• a processor operable to:
• receive a design data representing said IC at a logic level, said integrated circuit containing a plurality of memory elements and a plurality of combination logics which together provide an intended utility of said IC in a functional mode, said plurality of memory elements further being configurable to form a set of scan chains in said test mode;
• identify a set of memory elements which are present in said set of scan chains, each of said set of memory elements being one of said plurality of types;
• replace each of said set of memory elements with a corresponding said new element, wherein the first path of the memory element is connected to a corresponding combination logic and the second path of the memory element being connected to a next memory element of the corresponding scan chain;
• and
• simulate a plurality of scan tests on said IC with said set of new elements.