Hierarchical power map for low power design

A computer-implemented method for debugging the power aspect of an IC design specified in a power specification format by displaying a power map that integrates the power specification and its corresponding circuit design, the method comprising using a computer to perform the steps of:

• a. generating a knowledge data base from the circuit design when the computer is invoked to debug the IC design;
• b. generating a power data base according to the power specification and the knowledge data base;
• c. generating and displaying the power map by using the power data base, wherein the power map comprises a plurality of power domains each being associated with a different part of the circuit design;
• and
• d. checking and displaying the mismatches or errors according to the power specification and the circuit design for those signals connecting the power domains, wherein step d further comprises the sub-steps of:
• d1. if there are HDL signals between any two power domains and there are not any isolation connections between them, the power map will display a named virtual isolation connection net between the two power domains;
• and
• d2. if there are HDL signals between any two power domains and there are not any level shifter connections between them, the power map will display a named virtual level shifter connection net between the two power domains.