Hierarchical finite state machine generation for power state behavior in an electronic design
AssigneeMentor Graphics Corporation
InventorsPankaj Kumar Dwivedi, Amit Srivastava, Sachin Kakkar, Rudra Mukherjee
Life of this patent
Estimating the term…
Abstract
The invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine, representing the power behavior of an electronic design is extracted from the power specification for the electronic design. Subsequently, a hierarchical finite state machine representation for the power behavior is generated from the flat finite state machine, the power specification and the logical specification.
Claims20
A method comprising:
- generating, by a computing system, a flat finite state machine representation of at least a portion of an electronic design based, at least in part, on power state information described in a power specification of the electronic design;
- identifying, by the computing system, relationships between power states, between transitions associated with the power states, or between at least one of the power states and at least one of the transitions associated with the power states in the flat finite state machine representation based, at least in part, on the power specification and a logical specification corresponding to at least the portion of the electronic design;
- and
- generating, by the computing system, a hierarchical finite state machine representation of at least the portion of the electronic design based, at least in part, on the flat finite state machine representation and the identified relationships.
An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
- extracting power state information from a power specification of an electronic design, wherein the power state information includes power states and transitions associated with the power states corresponding to at least a portion of the electronic design;
- identifying relationships between the power states, between the transitions associated with the power states, or between at least one of the power states and at least one of the transitions associated with the power states in the power state information based, at least in part, on a logical specification corresponding to at least the portion of the electronic design;
- and
- generating a hierarchical finite state machine representation of at least the portion of the electronic design based, at least in part, on the identified relationships in the power state information.
A system comprising:
- a memory system storing instructions;
- and
- a computing system having one or more processing devices, in response to executing the instructions, are configured to:
- generate a flat finite state machine representation of at least a portion of an electronic design based, at least in part, on power state information described in a power specification of the electronic design;
- identify relationships between power states, between transitions associated with the power states, or between at least one of the power states and at least one of the transitions associated with the power states in the flat finite state machine representation based, at least in part, on the power specification and a logical specification corresponding to at least the portion of the electronic design;
- and
- generate a hierarchical finite state machine representation of at least the portion of the electronic design based, at least in part, on the flat finite state machine representation and the identified relationships.
Dependencies are inferred from the claim text.