Model based analog block coverage system
AssigneeCadence Design Systems, Inc.
InventorsWalter Hartong, Paul Christopher Foster, Jinduo Sun
Life of this patent
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AssigneeCadence Design Systems, Inc.
InventorsWalter Hartong, Paul Christopher Foster, Jinduo Sun
Estimating the term…
A system, method, and computer program product for automatically providing circuit designers with verification coverage information for analog/mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to assemble a schematic representation of a lower-level circuit design from pre-defined building blocks and various types of connections. Embodiments convert the schematic representation into a behavioral model for rapid simulation. Building blocks in the behavioral circuit have coverage-related terms defined either by the designer or by default, such as input and output value ranges, internal state changes, and state timers and timing-related constraints. Embodiments simulate the behavioral circuit, and determine and tangibly output coverage-related information. Manual and automatic behavioral circuit and stimulus modification can maximize coverage for improved behavioral circuit verification. Corresponding improvements to the underlying circuit may result, along with greatly reduced and better focused design and simulation efforts.
A computer-implemented method for verifying a circuit design, the method comprising:
A non-transitory computer readable medium storing instructions that, when executed by a processor, perform a method for verifying a circuit design comprising:
A system for verifying a circuit design, comprising:
Dependencies are inferred from the claim text.