Method and apparatus of enabling direct memory access into a target system memory modeled in dual abstractions while ensuring coherency

A functional verification system, comprising:

• a host workstation that includes:
• a workstation memory to store a plurality of memory pages modeled in a first design abstraction, and
• a processor to run a processor model in the first design abstraction, the processor model configured to run a first agent that can invoke a first method to access a modeled memory page of the plurality of memory pages until the first agent detects that a second agent, configured to run in a second design abstraction in an emulation hardware device, has requested access to a shadow copy of the modeled memory page, whereupon the first method is disabled and the first agent can invoke a second method to access the modeled memory page, wherein each memory page of the plurality of memory pages are accessible to the agent in the first design abstraction using the first method and the second method;
• and
• a communication link adapted to connect the emulation hardware device to the host workstation, wherein the communication link can transport a message to indicate that the second agent has requested access to the shadow copy.

A computer-readable non-transitory storage medium having stored thereon a plurality of instructions, the plurality of instructions when executed by a computer, cause the computer to perform:

• enabling a first method for an agent to access a memory page of a memory subsystem in a functional verification system that uses a plurality of design abstractions, wherein the memory page is one of a plurality of memory pages modeled in a first design abstraction of the plurality of design abstractions within a host workstation of the functional verification system, and wherein each memory pages is accessible to the agent in the first design abstraction using the first method and the second method;
• receiving an access request from an agent in a second design abstraction of the plurality of design abstractions to access a shadow memory page that is one of a plurality of shadow memory pages, wherein each shadow memory page is an image of one of the plurality of memory pages and is modeled in the second design abstraction within an emulation hardware device of the functional verification system;
• disabling the first method for the agent in the first design abstraction upon receipt of the access request;
• and
• enabling a second method for the agent in the first design abstraction to access the memory page upon receipt of the request.