Method and apparatus for synthesising a sum of addends operation and an integrated circuit
AssigneeImagination Technologies Limited
InventorsTheo Alan Drane, Thomas Rose
Life of this patent
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Abstract
A method is provided for a synthesizing In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimization constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined (20). Next, the maximum number of whole columns that can be removed from the sum of addends array is derived (22) and those columns are discarded (24). Next, a number of bits which can be removed from the least significant column is derived (26) and these bits are discarded (28). The constant is included in the sum of addends and a logic array synthesized in RTL (31) before manufacturing an integrated circuit.
Claims12
A machine-implemented method for deriving an Register Transfer Language (RTL) representation of a logic circuit for performing a sum of addends operation with faithful rounding, comprising:
- a) determining, in a computing system, a number of bits to discard from a result of the sum of addends to produce a faithfully rounded result;
- b) determining, in the computing system, a value of bits which may be discarded prior to performing the sum of addends operation and a constant to include in the sum of addends operation;
- c) determining, in the computing system, how many least significant whole columns of bits may be discarded from the sum of addends operation;
- d) discarding, in the computing system, those said columns;
- e) determining, in the computing system, how many bits of a next least significant column can be discarded from the sum of addends operation;
- f) discarding, in the computing system, those said bits from said next least significant column;
- and
- g) deriving, in the computing system, an RTL representation of the sum of addends operation with said truncated columns and bits, and including said constant.
An integrated circuit for performing multiplication of values to a predetermined faithful rounding precision comprising:
- an input to receive values;
- and
- a logic gate array to perform multiplication of the values and for providing an output value to the predetermined faithful rounding precision,
- wherein the logic gate array is configured to perform a sum of addends representing the multiplication, the sum of addends including columns of lower significance than the predetermined faithful rounding precision and wherein the logic gate array is further configured to sum only some of the bits of a least significant column of the said columns of lower significance.
A non-transitory computer program product embodying data in a hardware description language representation, the data describing an integrated circuit for performing multiplication of values to a predetermined faithful rounding precision, the described integrated circuit comprising:
- an input to receive values;
- a logic gate array to perform multiplication of the values and for providing an output value to the predetermined faithful rounding precision,
- wherein the logic gate array is configured to perform a sum of addends representing the multiplication, the sum of addends including columns of lower significance than the predetermined faithful rounding precision and wherein the logic gate array is further configured to sum only some of the bits of a least significant column of the said columns of lower significance, wherein the data in the hardware description language representation is readable by a computer in order to produce a description of a specific integrated circuit realization of the integrated circuit described by the data in the hardware description language representation thereof.
A non-transitory computer program product which when run on a computing system causes the computing system to perform a method for deriving an RTL representation of a logic circuit for performing a sum of addends operation with faithful rounding, the method comprising:
- a) determining a number of bits to discard from a result of the sum of addends to produce a faithfully rounded result;
- b) determining a value of bits which may be discarded prior to performing the sum of addends operation and a constant to include in the sum of addends operation;
- c) determining how many least significant whole columns of bits may be discarded from the sum of addends operation;
- d) discarding those said columns;
- e) determining how many bits of a next least significant column can be discarded from the sum of addends operation;
- f) discarding those said bits from said next least significant column;
- and
- g) deriving an RTL representation of the sum of addends operation without said discarded columns and bits, and including said constant.
A method used in producing an integrated circuit, comprising:
- providing a non-transitory machine readable medium for use by a computing system, on which is stored data representing a Register Transfer Language (RTL) representation of a logic circuit for performing a sum of addends operation with faithful rounding, the RTL representation of the logic circuit produced by a method comprising:
- determining a number of bits to discard from a result of the sum of addends to produce a faithfully rounded result;
- determining a value of bits which may be discarded prior to performing the sum of addends operation and a constant to include in the sum of addends operation;
- determining how many least significant whole columns of bits may be discarded from the sum of addends operation;
- discarding those said columns;
- determining how many bits of a next least significant column can be discarded from the sum of addends operation;
- discarding those said bits from said next least significant column, wherein the derived RTL representation of the sum of addends operation does not include logic for said discarded columns and bits, and includes said constant;
- and
- producing in the computing system a hardware description language representation of the RTL representation, the hardware description language representation describing hardware comprising
- an input to receive values;
- and
- a logic gate array to perform multiplication of the values and for providing an output value to the predetermined faithful rounding precision,
- wherein the logic gate array is configured to perform a sum of addends representing the multiplication, the sum of addends including columns of lower significance than the predetermined faithful rounding precision and wherein the logic gate array is further configured to sum only some of the bits of a least significant column of the said columns of lower significance.
Dependencies are inferred from the claim text.