Viterbi butterfly operations
AssigneeTexas Instruments Incorporated
InventorsProhor Chowdhury, Alexander Tessarolo
Life of this patent
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Abstract
A decoding system suitable for Viterbi decoding includes a decoder that includes a state metrics array, a butterfly unit, and a constraint length multiplexer. The state metrics array includes registers in which each register is arranged to store a state metric for processing. The butterfly unit includes an array of butterfly elements where each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit. The constraint length multiplexer unit is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register. Transition bits can also be generated in response to the constraint length.
Claims12
A processor, comprising
- a state metrics array having registers in which each register is arranged to store a state metric for processing;
- a butterfly unit that includes an array of butterfly elements wherein each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit;
- wherein each butterfly element is arranged to generate intermediate transition bits in parallel with other butterfly elements in the butterfly unit;
- a constraint length multiplexer unit that is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register;
- and
- a transition bits multiplexer unit that is arranged to generate the new state metrics in response to the intermediate transition bits and the Viterbi constraint length value stored in a constraint length register.
A communication system, comprising
- a decoder that includes a state metrics array having registers in which each register is arranged to store a state metric for processing, a butterfly unit that includes an array of butterfly elements wherein each butterfly element is arranged to generate intermediate state metrics in parallel with other butterfly elements in the butterfly unit, and a constraint length multiplexer unit that is arranged to generate new state metrics in response to the intermediate state metrics and a Viterbi constraint length value stored in a constraint length register;
- wherein each butterfly element is arranged to generate intermediate transition bits in parallel with other butterfly elements in the butterfly unit;
- a processor that is arranged to perform a Viterbi decoding process using the decoder to perform Viterbi decoding stages;
- a substrate in which the decoder and processor are arranged;
- and
- a transition bits multiplexer unit that is arranged to generate new state metrics in response to the intermediate transition bits and a Viterbi constraint length value stored in a constraint length register.
Dependencies are inferred from the claim text.