Peel decoding for concatenated codes

#FIG. 1 is a diagram showing an example of data encoded using concatenated codes in a storage system. In the example shown, a set of first codewords 100 is associated with a first error correction code (C1). Data portion 102 and parity portion 104 form a set of third codewords which is associated with a third error correction code (C3). To save space on the storage system, codewords 100 and parity portion 104 are stored, but data 102 (shaded) is not stored.

#If the error correction capability of the first code (C1) fails, parity 104 is read from storage and is used in correcting those codewords from 100 that were not able to be corrected using the first code (C1). Some other decoding techniques do this by estimating or synthesizing data portion 102. However, estimating or synthesizing data portion 102 has some drawbacks. For one, estimated values for data portion 102 are typically not fed into certain read processor components, such as Viterbi decoders, because the estimates may be bad estimates which cause a Viterbi decoder to make decisions it should not. More generally, estimates may cause new errors to be introduced into the system and thus should not be fed to Viterbi decoders and other components. Another drawback is that these estimation techniques may be computationally intensive, requiring many processing cycles. New techniques for decoding concatenated codes which overcome at least some of these drawbacks would be desirable.

#Various embodiments of the invention are disclosed in the following detailed description and the accompanying drawings.

#FIG. 1 is a diagram showing an example of data encoded using concatenated codes in a storage system.

#FIG. 2A is a diagram showing an embodiment of a concatenated encoding process.

#The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer readable storage medium; and/or a processor, such as a processor configured to execute instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being configured to perform a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ refers to one or more devices, circuits, and/or processing cores configured to process data, such as computer program instructions.

#A detailed description of one or more embodiments of the invention is provided below along with accompanying figures that illustrate the principles of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims and the invention encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.

#FIG. 2A is a diagram showing an embodiment of a concatenated encoding process. In the example shown, a first error correction code (C1) has a code rate of {n1=40,000, k1=36,000} in diagram 210. Input data which is 36,000 bits long is encoded to create codewords which are 40,000 bits long. The C1 codewords are grouped in groups of 100 codewords (i.e., m=100). It is not a requirement for the first error correction code to be a systematic code.