NAND memory management

#The present disclosure generally relates to the field of electronics. More particularly, some embodiments of the invention generally relate to error control codes and mapping techniques for three (3) level NAND flash memory.

#NAND memory is a type of flash memory that is non-volatile. NAND memory may be used in memory cards, flash drives, solid-state drives, and other memory products. Flash memory has a limitation on the number of erase/rewrite cycles, before it becomes unusable, or a finite number of program-erase cycles (typically written as P/E cycles). This finite limitation is sometimes referred to as the “erase endurance” or simply as “endurance” of a flash memory device.

#Flash memory may be designed using single-level cells (SLCs), which store a single bit of information in each memory cell, or as multi-level cells (MLCs), which store multiple bits of information in each memory cell. In general, single-level cells have higher endurance than multi-level cells. However, multi-level cells provide higher storage density than single-level cells.

#The detailed description is provided with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.

#FIG. 1 is a schematic, block diagram illustration of an electronic device which may be adapted to implement NAND memory management in accordance with various embodiments discussed herein.

#FIG. 2 is a schematic, block diagram illustration of components of an apparatus to implement NAND memory management in accordance with various embodiments discussed herein.

#In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, various embodiments of the invention may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments of the invention. Further, various aspects of embodiments of the invention may be performed using various means, such as integrated semiconductor circuits (“hardware”), computer-readable instructions organized into one or more programs (“software”), or some combination of hardware and software. For the purposes of this disclosure reference to “logic” shall mean either hardware, software, or some combination thereof.

#Mapping an binary string onto a NAND memory device which is programmed to n-levels, where n is a power of 2, is relatively straightforward. However, mapping a binary string onto a NAND memory device which is programmed to n-levels, where n is not a multiple of 2, raises issues with respect to both mapping and error correction. The subject matter described herein provides techniques to address both mapping and error correction issues for programming n-level NAND devices where n is not a multiple of 2.

#The techniques discussed herein may be provided in various computing systems (e.g., including smart phones, tablets, portable game consoles, etc. FIG. 1 is a schematic, block diagram illustration of an electronic device which may be adapted to implement NAND memory management in accordance with various embodiments discussed herein. Referring to FIG. 1, a system 100 may include one or more processors 102-1 through 102-N (generally referred to herein as “processors 102” or “processor 102”). The processors 102 may communicate via an interconnection or bus 104. Each processor may include various components some of which are only discussed with reference to processor 102-1 for clarity. Accordingly, each of the remaining processors 102-2 through 102-N may include the same or similar components discussed with reference to the processor 102-1.