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US 8,943,379 B2Granted
Retry based protocol with source/receiver FIFO recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction
AssigneeIntel Corporation
InventorsJames R. Vash, Danielle N. Devereaux, Scott J. Erlanger, Robert E. Faber
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Abstract
Methods and apparatus relating to retry based protocol with source/receiver FIFO (First-In, First-Out) buffer recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction are described. In an embodiment, upon detection of an error, a portion of transmitted data is stored in one or more storage devices before retransmission. Other embodiments are also described and claimed.
Claims11
An apparatus, comprising:
- a processor having a cache, a plurality of processing cores and a network between said cache and said processing cores, said cache to provide cached data to any of said processing cores, wherein, circuitry to send cached data to its respective processing core includes an ECC unit, a buffer and a bypass that circumvents said buffer, said buffer to queue requested cached data and its destination and header information between said cache and said network, said bypass to send said requested cached data's destination and header information to its respective processing core without delay imposed by said buffer, wherein, upon said ECC unit providing an indication that said requested cached data is corrupted after it is too late to prevent said requested cached data's destination and header information from being sent into said network, said circuitry:
- marks said requested cached data with a retry bit and forwards said requested cached data towards said network;
- and
- prevents other requested cached data from being entered into said buffer for a predetermined number of cycles following said indication.
1 more element
A method, comprising:
- processing requested cached data at a cache end by:
- sending destination and header information for said requested cache data into a network by by-passing a buffer designed to impose delay between a cache where said requested cache data is cached and said network;
- raising an indication that said requested cache data is corrupted after it is too late to prevent said sending;
- marking said requested cached data with a retry bit and forwarding said requested cached data toward said network;
- preventing other requested cached data from entering said buffer for a predetermined number of cycles after said raising.
2 more elements
Dependencies are inferred from the claim text.