Combo static flop with full test

A semiconductor device comprising:

• a mechanical package;
• and
• a semiconductor die comprising:
• a semiconductor layer,
• a plurality of metal layers,
• a clock distribution network that distributes a clock signal within the die, and
• a SRAM (Static Random Access Memory) macro test flop circuit, driven by a source clock signal, comprising:
• a flip-flop circuit comprising:
• a master latch circuit comprising:
• a master storage node, and
• a three to one multiplexer with a first data-in, a second data-in, and a third data-in as three multiplexer inputs, wherein the multiplexer output provides a control signal for writing to the master storage node, and
• a slave latch circuit comprising:
• a slave storage node, and
• wherein the slave latch is operatively driven from the master latch, and
• wherein the master latch provides a control signal for writing to the slave storage node,
• wherein the master latch is precharged while data is preserved in the slave latch until a next clock cycle,
• a scan control circuit comprising:
• a scan slave feed-forward circuit providing a control signal for writing scan data to the slave storage node,
• a scan latch circuit comprising:
• a scan feed-back circuit comprising a scan storage node,
• a scan feed-forward circuit operatively driven from the slave latch, wherein the scan feed-forward circuit provides control signal for writing to the scan storage node, and
• a scan driver, with a scan output port, operatively driven by the scan feed-back circuit, and
• an output buffer circuit.

A system comprising:

• an input device;
• an output device;
• a mechanical chassis;
• a printed circuit board;
• and
• a semiconductor device comprising:
• a mechanical package;
• and
• a semiconductor die comprising:
• a semiconductor layer,
• a plurality of metal layers,
• a clock distribution network that distributes a clock signal within the die, and
• a SRAM (Static Random Access Memory) macro test flop circuit, driven by a source clock signal, comprising:
• a flip-flop circuit comprising:
• a master latch circuit comprising:
• a master storage node, and
• a three to one multiplexer with a first data-in, a second data-in, and a third data-in as three multiplexer inputs, wherein the multiplexer output provides a control signal for writing to the master storage node, and
• a slave latch circuit comprising:
• a slave storage node, and
• wherein the slave latch is operatively driven from the master latch, and
• wherein the master latch provides a control signal for writing to the slave storage node,
• wherein the master latch is precharged while data is preserved in the slave latch until a next clock cycle,
• a scan control circuit comprising:
• a scan slave feed-forward circuit providing a control signal for writing scan data to the slave storage node,
• a scan latch circuit comprising:
• a scan feed-back circuit comprising a scan storage node,
• a scan feed-forward circuit operatively driven from the slave latch, wherein the scan feed-forward circuit provides control signal for writing to the scan storage node, and
• a scan driver, with a scan output port, operatively driven by the scan feed-back circuit, and
• an output buffer circuit.