Controlling the power state of an idle processing device
AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsOleksandr Khodorkovsky, Paul Blinzer, Korhan Erenben, Leonard Martin Berk, Min Zhang
Life of this patent
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Abstract
A method of operating a processing device is provided. The method includes, responsive to an idle state of the processing device, transitioning the processing device to a substantially disabled state. The processing device, for example, may be a graphics processing unit (GPU). Transitioning the processing device to a substantially disabled state upon detection of an idle state may result in power savings. Corresponding systems and computer program products are also provided.
Claims18
A method comprising:
- detecting an idle state of a primary processing device;
- detecting a substantially disabled state for one or more secondary processing devices;
- and
- transitioning the primary processing device to a substantially disabled state in response to the detecting of the idle state and to the detecting of the substantially disabled state for the one or more of the secondary processing devices,
- wherein the primary processing device generates a first response signal in response to a first received bus configuration cycle signal when the primary processing device is in the substantially disabled state,
- wherein the first response signal is substantially similar to a second response signal generated by the primary processing device in response to a second received bus configuration cycle when the primary processing device is in an operational state.
A system, comprising:
- a primary processing device;
- a power manager configured to:
- detect an idle state of the processing device;
- detect a substantially disabled state for one or more secondary processing devices;
- and
- transition the primary processing device to a substantially disabled state in response to the detection of the idle state and to the detecting of the substantially disable state for the one or more of the secondary processing devices;
- and
- a bus interface, comprising a response module configured to generate a first response signal in response to a first received bus configured cycle signal when the primary processing device is in the substantially disabled state, the first response signal being substantially similar to a second response signal generated by the primary processing device in response to a second received bus configuration cycle when the primary processing device is in an operational state.
A non-transitory computer readable medium having one or more instructions recorded thereon, execution of which by a processor cause the processor to perform operations comprising:
- detecting an idle state of a primary processing device;
- detecting a substantially disabled state for one or more secondary processing devices;
- and
- transitioning the primary processing device to a substantially disabled state in response to the detecting of the idle state and to the detecting of the substantially disabled state for the one or more of the secondary processing devices,
- wherein the primary processing device generates a first response signal in response to a first received bus configuration cycle signal when the primary processing device is in the substantially disabled state,
- wherein the first response signal is substantially similar to a second response signal generated by the primary processing device in response to a second received bus configuration cycle when the primary processing device is in an operational state.
Dependencies are inferred from the claim text.