Controlling an asymmetrical processor

A method comprising:

• querying, via an arbitration unit of a multicore processor including a first core having a first power consumption level and a second core having a second power consumption level greater than the first power consumption level, a memory controller of the multicore processor coupled to a first memory device to be used by the first core and a second memory device to be used by the second core, for a memory utilization level of the second memory device;
• determining whether the memory utilization level is less than a memory utilization threshold;
• and
• if so, causing the second core to enter into a low power state while maintaining the first core powered on.

A system comprising:

• a multicore processor including a front end unit having a fetch unit to fetch instructions and a decode unit to decode the fetched instructions into decoded instructions, a first core coupled to the front end unit to independently execute at least some of the decoded instructions, the first core having a first power consumption level, a second core coupled to the front end unit to independently execute at least some of the decoded instructions, the second core having a second power consumption level greater than the first power consumption level and heterogeneous from the first core, and a memory controller to interface with a first memory device to be used by the first core and a second memory device to be used by the second core;
• the first memory device coupled to the multicore processor to operate at a first speed;
• and
• the second memory device coupled to the multicore processor to operate at a second speed.