Storing branch information in an address table of a processor

A method, in a processor of a data processing system, for performing branch operations, comprising:

• fetching, by an instruction fetch unit of the processor, an instruction to be executed;
• retrieving, from a single address table structure of the processor, instruction information for the fetched instruction;
• and
• performing, by a branch execution unit of the processor, a branch operation based on the received instruction and the instruction information retrieved from the single address table structure of the processor;
• and
• invalidating an address table entry in the single address table structure in response to execution of all instructions corresponding to the address table entry being completed, wherein:
• the single address table structure comprises address table entries, each address table entry corresponding to one or more instructions to be executed by the processor and simultaneously storing both address information and branch prediction information for the one or more instructions, and
• the single address table structure is coupled to, and shared by, both the instruction fetch unit and the branch execution unit.

An apparatus, comprising:

• an instruction fetch unit that is configured to fetch an instruction to be executed;
• a single address table structure coupled to the fetch unit;
• and
• a branch execution unit coupled to the single address table structure, wherein the branch execution unit is configured to:
• retrieve, from the single address table structure, instruction information for the fetched instruction;
• and
• perform a branch operation based on the received instruction and the instruction information retrieved from the single address table structure of the processor, wherein:
• the single address table structure comprises address table entries, each address table entry corresponding to one or more instructions to be executed by the processor and simultaneously storing both address information and branch prediction information for the one or more instructions, and
• the single address table structure is coupled to, and shared by, both the instruction fetch unit and the branch execution unit, and wherein the branch execution unit performs the branch operation based on the received instruction and the instruction information retrieved from the single address table structure of the processor by determining a predicted target address for a branch instruction of a first address table entry in the single address table structure based on a base address of a next address table entry in the single address table structure, in response to the first address table entry comprising branch information indicating the branch instruction to be predicted to be taken.

An apparatus, comprising:

• an instruction fetch unit that is configured to fetch an instruction to be executed;
• a single address table structure coupled to the fetch unit;
• and
• a branch execution unit coupled to the single address table structure, wherein the branch execution unit is configured to:
• retrieve, from the single address table structure, instruction information for the fetched instruction;
• and
• perform a branch operation based on the received instruction and the instruction information retrieved from the single address table structure of the processor, wherein:
• the single address table structure comprises address table entries, each address table entry corresponding to one or more instructions to be executed by the processor and simultaneously storing both address information and branch prediction information for the one or more instructions,
• the single address table structure is coupled to, and shared by, both the instruction fetch unit and the branch execution unit, and wherein both the instruction fetch unit and branch execution unit directly access the single address table structure, and
• the apparatus is configured to invalidate an address table entry in the single address table structure in response to execution of all instructions corresponding to the address table entry being completed.

A computer program product for performing branch operations, the computer program product comprising:

• a non-transitory computer readable storage medium;
• first program instructions to fetch an instruction to be executed;
• second program instructions to retrieve, from a single address table structure, instruction information for the fetched instruction;
• and
• third program instructions to perform a branch operation based on the received instruction and the instruction information retrieved from the single address table structure of the processor, wherein the first, second, and third program instructions are stored on the computer readable storage medium, and wherein:
• the single address table structure comprises address table entries, each address table entry corresponding to one or more instructions to be executed by the processor and simultaneously storing both address information and branch prediction information for the one or more instructions, and
• the single address table structure is coupled to, and shared by, both the instruction fetch unit and the branch execution unit, and wherein performing the branch operation based on the received instruction and the instruction information retrieved from the single address table structure of the processor further comprises determining a predicted target address for a branch instruction of a first address table entry in the single address table structure based on a base address of a next address table entry in the single address table structure, in response to the first address table entry comprising branch information indicating the branch instruction to be predicted to be taken.