Virtual address mapping using rule based aliasing to achieve fine grained page translation
AssigneeVMware, Inc.
InventorsBenjamin C. Serebrin, Bhavesh Mehta
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Abstract
One or more unused bits of a virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.
Claims15
A method of translating virtual addresses to physical memory pages in a computer system, comprising:
- receiving a first binary representation of a virtual address to be translated;
- modifying the first binary representation to generate a second binary representation by copying M bit values from bit position N through bit position N−(M−1) of the first binary representation to bit position L through bit position L−(M−1) of the first binary representation, wherein the bit position L is more significant than the bit position N and M is at least one;
- and
- if the bit value at the bit position N is 0, traversing a first set of page tables using the second binary representation to obtain a first page table entry that points to a first physical memory page;
- and
- if the bit value at the bit position N is 1, traversing a second set of page tables, which is different from the first set of page tables, using the second binary representation to obtain a second page table entry that points to the first physical memory page.
A non-transitory computer readable storage medium embodying software instructions for causing a computer system to carry out a method for translating virtual addresses to physical memory pages, the method comprising:
- receiving a first binary representation of a virtual address to be translated;
- modifying the first binary representation to generate a second binary representation by copying M bit values from bit position N through bit position N−(M−1) of the first binary representation to bit position L through bit position L−(M−1) of the first binary representation, wherein the bit position L is more significant than the bit position N and M is at least one;
- and
- if the bit value at the bit position N is 0, traversing a first set of page tables using the second binary representation to obtain a first page table entry that points to a first physical memory page;
- and
- if the bit value at the bit position N is 1, traversing a second set of page tables, which is different from the first set of page tables, using the second binary representation to obtain a second page table entry that points to the first physical memory page.
A virtualized computer system supported by a hardware platform that includes one or more physical CPUs and a physical system memory, the virtualized computer system comprising:
- a plurality of virtual machines;
- and
- a hypervisor that includes a plurality of virtual machine monitors, wherein each virtual machine monitor supports one of the virtual machines and is configured to perform virtual to physical address translations for the virtual machine that the hypervisor supports, and wherein performing a virtual to physical address translation includes:
- receiving a first binary representation of a virtual address to be translated;
- modifying the first binary representation to generate a second binary representation by copying M bit values from bit position N through bit position N−(M−1) of the first binary representation to bit position L through bit position L−(M−1) of the first binary representation, wherein the bit position L is more significant than the bit position N and M is at least one;
- and
- if the bit value at the bit position N is 0, traversing a first set of page tables using the second binary representation to obtain a first page table entry that points to a first physical memory page;
- and
- if the bit value at the bit position N is 1, traversing a second set of page tables, which is different from the first set of page tables, using the second binary representation to obtain a second page table entry that points to the first physical memory page.
Dependencies are inferred from the claim text.