US 8,943,292 B2Granted

System and method for memory array access with fast address decoder

AssigneeFreescale Semiconductor, Inc.

InventorsRavindraraj Ramaraju, David R. Bearden, Prashant U. Kenkare

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Abstract

A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.

Claims6

Dependent claims

A method of operating a memory having a wordline driver, a first array, a second array, a third array, and a fourth array, comprising:

summing a first set of bits of a first operand and a corresponding set of bits of a second operand to obtain a pair of selection bits;
providing a first plurality of bits of the first operand;
providing a second plurality of bits of the second operand;
providing a third plurality of bits of the first operand;
providing a fourth plurality of bits of the second operand;
decoding a value that is based on the first plurality of bits and the second plurality of bits to provide a first decoded value to the wordline driver;
decoding a value that is based on the first plurality of bits and the second plurality of bits to provide a second decoded value to the wordline driver;
decoding a value that is based on the third plurality of bits and the fourth plurality of bits to provide a third decoded value to the wordline driver;
decoding a value that is based on the third plurality of bits and the fourth plurality of bits to provide a fourth decoded value to the wordline driver;
using the wordline driver to enable a wordline of the first array selected by the first and third decoded values, a wordline of the second array selected by the first and fourth decoded values, a wordline of the third array selected by the second and third decoded values, and a wordline of the fourth array selected by the second and fourth decoded values;and
using the pair of selection bits to select one of the first, second, third, and fourth arrays for providing an output corresponding to the sum of the first set of bits and the corresponding set of bits.

8 more elements

A data processing system for providing a TAG having a memory comprising a wordline driver, a first array, a second array, a third array, and a fourth array, comprising:

an adder that adds a first plurality of bits that comprise a subset of a first operand to a second plurality of bits that comprise a subset of a second operand and provides a selection set of bits that is fewer in number than the first plurality of bits;
a first decoder coupled to receive a first set of bits that is a subset of the first plurality of bits and a second set of bits that is a subset of the second plurality of bits, and coupled to provide a first decoded value based on the first set of bits and the second set of bits and a second decoded value based on the first set of bits and the second set of bits;
and
a second decoder coupled to receive a third set of bits of that is a subset of the first plurality of bits and a fourth set of bits that is a subset of the second plurality of bits, and coupled to provide a third decoded value based on the third set of bits and the fourth set of bits and a fourth decoded value based on the third set of bits and the fourth set of bits;
and
a multiplexer coupled to the first, second, third, and fourth arrays and receives the selection set of bits;
wherein:
the wordline driver is coupled to receive the first decoded value, the second decoded value, the third decoded value, and the fourth decoded value, and coupled to enable one wordline of each of the first, second, third, and fourth arrays;
and
the multiplexer selects one of the first, second, third, and fourth arrays for providing the TAG.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/552,817Filed 25 Oct 2006 · continuation in part
Priority: 25 Oct 2005
Published: US 2007/0094479 A126 Apr 2007
Granted: 27 Jan 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 9/355
Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes: indexed addressing
G06F 9/345
Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes: of multiple operands or results
G06F
Computing and data processing

Family

Application11/257,932Parent of this continuation-in-part · filed 25 Oct 2005
US 2007/0094480 A1Pre-grant publication · published 26 Apr 2007
US 7,669,034 B2Parent of this continuation-in-part
US 2007/0094479 A1Published application
US 8,943,292 B2This patent

From the US filing history. Foreign family members aren’t listed.