US 8,943,287 B1Granted

Multi-core processor system configured to constrain access rate from memory

AssigneeRockwell Collins, Inc.

InventorsDavid A. Miller, David C. Matthews

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Abstract

A multi-core processor system includes a number of cores, a memory system, and a common access bus. Each core includes a core processor; a dedicated core cache operatively connected to the core processor; and, a core processor rate limiter operatively connected to the dedicated core cache. The memory system includes physical memory; a memory controller connected to the physical memory; and, a dedicated memory cache connected to the memory controller. The common access bus interconnects the cores and the memory system. The core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value.

Claims18

Dependent claims

A multi-core processor system, comprising:

a) a plurality of cores, each core comprising;
i) a core processor;
ii) a dedicated core cache operatively connected to the core processor;
and,
iii) a core processor rate limiter operatively connected to the dedicated core cache;
b) a memory system, comprising:
i) physical memory;
ii) a memory controller connected to the physical memory;
and,
iii) a dedicated memory cache connected to the memory controller;
and,
c) a common access bus for interconnecting said plurality of cores and said memory system,
wherein said core processor rate limiters are configured to constrain the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value, wherein each core processor memory access comprises an individual cache line memory access, and wherein each core processor rate limiter utilizes a token bucket process, said token bucket process including a) waiting until a core memory access count is reached following an initialization setting, wherein event counters in each core processor rate limiter are set to a predetermined value;
b) determining a memory access envelope eligibility time (ET) when the core memory access count is reached;
and c) waiting until said ET is reached.

12 more elements

A multi-core processor system, comprising:

a) a plurality of cores, each core comprising;
i) a core processor;
ii) a dedicated core cache operatively connected to the core processor;
and,
iii) a core processor rate limiter operatively connected to the dedicated core cache;
b) a memory system, comprising:
i) physical memory;
ii) a memory controller connected to the physical memory;
and,
iii) a dedicated memory cache connected to the memory controller;
c) a common access bus for interconnecting said plurality of cores and said memory system;
and,
d) at least one master controller system operatively connected to said common access bus capable of performing memory accesses over said common access bus, said master controller system comprising a master controller and a master controller rate limiter,
wherein said core processor rate limiter and said master controller rate limiter are configured to constrain the rate at which data is accessed by each respective core processor or master controller from the memory system so that each core processor or master controller memory access is capable of being limited to an expected value, wherein each core processor memory access comprises an individual cache line memory access, and wherein each core processor rate limiter utilizes a token bucket process, said token bucket process including a) waiting until a core memory access count is reached following an initialization setting, wherein event counters in each core processor rate limiter are set to a predetermined value;
b) determining a memory access envelope eligibility time (ET) when the core memory access count is reached;
and c) waiting until said ET is reached.

13 more elements

A method for operating a multi-core processor system, comprising the steps of:

a) providing a plurality of cores, each core comprising;
i) a core processor;
ii) a dedicated core cache operatively connected to the core processor;
and,
iii) a core processor rate limiter operatively connected to the dedicated core cache;
b) providing a memory system, comprising:
i) physical memory;
ii) a memory controller connected to the physical memory;
and,
iii) a dedicated memory cache connected to the memory controller;
c) providing a common access bus for interconnecting said plurality of cores and said memory system;
and,
d) constraining the rate at which data is accessed by each respective core processor from the memory system so that each core processor memory access is capable of being limited to an expected value,
wherein each core processor memory access comprises an individual cache line memory access, and wherein each core processor rate limiter utilizes a token bucket process, said token bucket process including a) waiting until a core memory access count is reached following an initialization setting, wherein event counters in each core processor rate limiter are set to a predetermined value;
b) determining a memory access envelope eligibility time (ET) when the core memory access count is reached;
and c) waiting until said ET is reached.

13 more elements

Dependencies are inferred from the claim text.