Method and apparatus for improving cache efficiency

A cache memory, comprising:

• a cache array;
• a buffer unit having a buffer entry, the buffer entry being in association with the cache array;
• and
• a control unit configured to
• store data in the buffer entry in response to a first store instruction that hits the cache array before the first store instruction is committed,
• speculatively bypass the data from the buffer entry in response to a first dependent load instruction, the first dependent load instruction being subsequent to the first store instruction, wherein speculatively bypassing the data from the buffer entry in response to the first dependent load instruction retrieves the data from the buffer entry without checking the cache array,
• coalesce data of a second store instruction that overlaps an address of the first store instruction in the buffer entry before the second store instruction is committed,
• evict the buffer entry to store the data in the cache array if the second store instruction is committed after the first store instruction is committed, and
• clear the buffer entry if the first store instruction is committed and the second store instruction is aborted.

A computer system, comprising:

• a processor core configured to access a cache system in response to instructions;
• and
• the cache system having a backing memory and a cache unit, wherein the backing memory is configured to store data in response to store instructions that are committed, and the cache unit further comprises:
• a cache array;
• a buffer unit having at least a buffer entry in association with the cache array;
• and
• a control unit configured to
• store data in the buffer entry in response to a first store instruction that hits the cache array before the first store instruction is committed,
• speculatively bypass the data from the buffer entry in response to a first dependent load instruction, the first dependent load instruction being subsequent to the first store instructions, wherein speculatively bypassing the data from the buffer entry in response to the first dependent load instruction retrieves the data from the buffer entry without checking the cache array,
• coalesce data of a second store instruction that overlaps an address of the first store instruction in the buffer entry before the second store instruction is committed,
• evict the buffer entry to store the data in the cache array if the second store instruction is committed after the first store instruction is committed, and
• clear the buffer entry if the first store instruction is committed and the second store instruction is aborted.