Latency sensitive software interrupt and thread scheduling
AssigneeMicrosoft Corporation
InventorsBradley M. Waters, Danyu Zhu
Life of this patent
Estimating the term…
Abstract
Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.
Claims20
A computer-implemented method comprising:
- receiving a software interrupt;
- responsive to receiving the software interrupt, determining whether the software interrupt is latency sensitive;
- responsive to determining the software interrupt is latency sensitive, determining whether a current processor core is interrupt heavy;
- responsive to determining the current processor core is interrupt heavy and that the software interrupt is latency sensitive, determining a desired processor core other than the current processor core to run the software interrupt;
- and
- responsive to determining the desired processor core other than the current processor core, executing the software interrupt on the desired processor core.
One or more computer readable storage devices embodying computer readable instructions which, when executed, implement a method comprising:
- preparing a software thread to run;
- determining whether the software thread is latency-sensitive;
- responsive to determining the software thread is latency-sensitive, gathering processor core usage information;
- determining a desired processor core to run the software thread based, at least in part, on the processor core usage information;
- and
- responsive to determining the desired processor core, running the software thread on said determined processor core.
A system comprising:
- one or more processor cores;
- one or more computer-readable storage media associated with the one or more processor cores;
- one or more processor core loading modules configured to:
- identify whether a task is latency-sensitive or not;
- identify one or more characteristics associated with the one or more processor cores;
- and
- assign the task to a processor core with available resources based at least in part, on whether the task is latency-sensitive or not and based, at least in part, on the one or more characteristics associated with the one or more processor cores.
Dependencies are inferred from the claim text.