Packet scheduling using a programmable weighted fair queuing scheduler that employs deficit round robin
AssigneeNetLogic Microsystems, Inc.
InventorOzair Usmani
Life of this patent
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AssigneeNetLogic Microsystems, Inc.
InventorOzair Usmani
Estimating the term…
The disclosed packet scheduler implements the deficit round robin (DRR) approximation of weighted fair queuing (WFQ), and is capable of achieving complete fairness across several hundred source flows, for example, each of which can be mapped to one of several destination ports. In addition to achieving fairness, the packet scheduler allows the user to map one or more optional strict-priority flows to each port. The packet scheduler keeps these strict-priority flows “outside” of the group of flows for which fairness is enforced. Each destination port can be optionally configured to chop its data packets into sub-packet pieces. The packet scheduler works in two mutually orthogonal dimensions: (1.) it selects destination ports based on a round-robin scheme, or using another method, such as guaranteed rate port scheduling (GRPS), and (2.) it implements optional strict-priority scheduling, and DRR scheduling.
A method for data packet scheduling, the method comprising:
A data packet scheduler comprising:
Dependencies are inferred from the claim text.