System and method to implement a matrix multiply unit of a broadband processor
AssigneeMicroUnity Systems Engineering, Inc.
InventorsCraig Hansen, Bruce Bateman, John Moussouris
Life of this patent
Estimating the term…
Abstract
A system and a method are configured to improve the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128 b by 128 b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.
Claims26
A system for multiplying matrix multiplicand data by vector multiplier data, the system comprising:
- a memory for storing the matrix multiplicand data and a register for storing the vector multiplier data, the matrix multiplicand data having a bit width wider than the vector multiplier data;
- a multiplier formatter coupled to the memory for receiving the vector multiplier data and partitioning it into a plurality of vector data elements;
- a multiplicand formatter coupled to the memory for receiving the matrix multiplicand data and partitioning it into a plurality of matrix multiplicands;
- a group of multiplier strips producing partial products;
- a group of alignment stages, each stage including a bit-aligning multiplexer;
- a group of reduction stages;
- a final carry propagation stage for providing a result of multiplication of the matrix multiplicand data by the vector multiplier data;
- and wherein:
- the matrix multiplicand data and the vector multiplier data include floating point data having exponents and significand fields;
- and
- each reduction stage aligns n-bit partial products to 2n-bit alignment thereby producing 2n-bit aligned partial products before adding the 2n-bit aligned partial products to produce a 2n-bit partial product.
In a multiplier unit of a processor a method for multiplying matrix multiplicand data by vector multiplier data, each of the matrix multiplicand data and the vector multiplier data including floating point data having exponents and significand fields, the method comprising:
- receiving the vector multiplier data and partitioning it into a plurality of vector data elements;
- receiving the matrix multiplicand data and partitioning it into a plurality of matrix multiplicands, the matrix multiplicand data having a bit width wider than that of the vector multiplier data;
- masking exponents of floating point data to exclude the exponents from the vector data elements and from the matrix multiplicand data;
- multiplying the vector data elements and the matrix multiplicands to produce n-bit partial products;
- aligning the n-bit partial products to 2n-bit alignment thereby producing 2n-bit aligned partial products;
- adding the 2n-bit aligned partial products to produce a 2n-bit partial product;
- and
- performing a carry propagation operation on the 2n-bit partial products to produce a result of multiplication of the matrix multiplicand data by the vector multiplier data.
Dependencies are inferred from the claim text.