Bitwise comparator for selecting two smallest numbers from a set of numbers

A method for determining, from among a group of values represented by a group of signals input to a circuit, which value in said group of values is a minimum value and which value in said group of values is a next-to-minimum value, said method comprising:

• making a series of comparisons to determine a minimum value and a next-to-minimum value out of four values, including comparing, in said circuit, respective signals representing a first two of said four values to determine a first minimum and a first maximum, and comparing respective signals representing a second two of said four values to determine a second minimum and a second maximum, each comparison in said series of comparisons comprising:
• comparing bitwise, in a first cascade of first bitwise comparators of said circuit, a signal representing said first minimum to a signal representing said second minimum, from most-significant bit to least-significant bit, each bitwise comparison of said signal representing said first minimum to said signal representing said second minimum providing a bit of a signal representing said minimum value out of said four values and a respective bit of a bitwise selection signal;
• comparing bitwise, in a second cascade of second bitwise comparators of said circuit, a signal representing said first maximum to said signal representing said second minimum, from most-significant bit to least-significant bit, each bitwise comparison of said signal representing said first maximum to said signal representing said second minimum providing a first respective candidate bit of a signal representing said next-to-minimum value out of said four values;
• comparing bitwise, in a third cascade of third bitwise comparators of said circuit, a signal representing said second maximum to said signal representing said first minimum, from most-significant bit to least-significant bit, each bitwise comparison of said signal representing said second maximum to said signal representing said first minimum providing a second respective candidate bit of said signal representing said next-to-minimum value out of said four values;
• and
• selecting between said first and second respective candidate bits of said signal representing said next-to-minimum value out of said four values in a set of respective multiplexers, each selection under control of said respective bit of said bitwise selection signal.

A low-density parity check decoder comprising:

• comparator circuitry for determining, from among four values, where a first two of said four values have been compared to determine a first minimum and a first maximum and a second two of said four values have been compared to determine a second minimum and a second maximum, which of said four values is a minimum value and which of said four values is a next-to-minimum value, said comparator circuitry comprising:
• a first cascade of first bitwise comparators for comparing said first minimum to said second minimum from most-significant bit to least-significant bit, each of said first bitwise comparators outputting a bit of said minimum value and a respective bit of a bitwise selection signal;
• a second cascade of second bitwise comparators for comparing said first maximum to said second minimum from most-significant bit to least-significant bit, each of said second bitwise comparators outputting a first respective candidate bit of said next-to-minimum value;
• a third cascade of third bitwise comparators for comparing said second maximum to said first minimum from most-significant bit to least-significant bit, each of said third bitwise comparators outputting a second respective candidate bit of said next-to-minimum value;
• and
• a set of respective multiplexers each having as data inputs said first and second respective candidate bits of said next-to-minimum value, and each having as a control input said respective bit of said bitwise selection signal.

A low-density parity check decoder comprising:

• comparator circuitry for determining which value in a group of values is a minimum value and which value in said group of values is a next-to-minimum value, said comparator circuitry comprising:
• a tree of comparator subcircuits each of which determines a minimum value and a next-to-minimum value out of four values, where a first two of said four values have been compared to determine a first minimum and a first maximum and a second two of said four values have been compared to determine a second minimum and a second maximum, each of said comparator subcircuits comprising:
• a first cascade of first bitwise comparators for comparing said first minimum to said second minimum from most-significant bit to least-significant bit, each of said first bitwise comparators outputting a bit of said minimum value out of said four values and a respective bit of a bitwise selection signal;
• a second cascade of second bitwise comparators for comparing said first maximum to said second minimum from most-significant bit to least-significant bit, each of said second bitwise comparators outputting a first respective candidate bit of said next-to-minimum value out of said four values;
• a third cascade of third bitwise comparators for comparing said second maximum to said first minimum from most-significant bit to least-significant bit, each of said third bitwise comparators outputting a second respective candidate bit of said next-to-minimum value out of said four values;
• and
• a set of respective multiplexers each having as data inputs said first and second respective candidate bits of said next-to-minimum value out of said four values, and each having as a control input said respective bit of said bitwise selection signal.