Method for implementing 32 bit complex multiplication by using 16-bit complex multipliers
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsEran Ovadia Mershain, Eran Goldstein
Life of this patent
Estimating the term…
Abstract
An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a first 2N-bit complex number and a second 2N-bit complex number, each having a first format, and to reformat the first and the second 2N-bit complex numbers to a second format such that a lower portion of each real and imaginary part of each 2N-bit complex number is positive. The second circuit may be configured to multiply the first and the second 2N-bit complex numbers using at least one N-bit signed complex multiplier, where N is an integer.
Claims20
An apparatus comprising:
- a first circuit configured to receive a first 2N-bit complex number and a second 2N-bit complex number, each having a first format in which each real and imaginary part of each 2N-bit complex number has a sign portion, comprising one or more most significant bits, and a magnitude portion, comprising all remaining bits, and to reformat the first and the second 2N-bit complex numbers to a second format such that each real and imaginary part of each reformatted 2N-bit complex number comprises a signed upper portion and a signed lower portion and the signed lower portion of each real and imaginary part of each reformatted 2N-bit complex number is positive;
- and
- a second circuit configured to multiply the reformatted first and the reformatted second 2N-bit complex numbers using at least one N-bit signed complex multiplier, wherein N is an integer.
A method of multiplying 2N-bit complex numbers using one or more N-bit signed complex multipliers comprising the steps of:
- receiving a first and a second 2N-bit complex number having a first format in which each real and imaginary part of each 2N-bit complex number has a sign portion, comprising one or more most significant bits, and a magnitude portion, comprising all remaining bits;
- reformatting the first and the second 2N-bit complex numbers to a second format such that each real and imaginary part of each reformatted 2N-bit complex number comprises a signed upper portion and a signed lower portion and the signed lower portion of each real and imaginary part of each reformatted 2N-bit complex number is positive;
- and
- multiplying the reformatted first and the reformatted second complex numbers using only one or more N-bit signed complex multipliers, wherein N is an integer and the one or more N-bit signed complex multipliers are implemented in hardware or a combination of hardware and software.
An apparatus comprising:
- means for receiving a first 2N-bit complex number and a second 2N-bit complex number, each having a first format in which each real and imaginary part of each 2N-bit complex number has a sign portion, comprising one or more most significant bits, and a magnitude portion, comprising all remaining bits, and reformatting the first and the second 2N-bit complex numbers to a second format such that (N+1) most significant bits of a real portion of each 2N-bit complex number are shifted one bit to the left, (N+1) most significant bits of an imaginary portion of each 2N-bit complex number are shifted one bit to the left, and each (N−1) bit of said real portion and said imaginary portion of each 2N-bit complex number is set to zero;
- and
- means for multiplying the reformatted first and the reformatted second 2N-bit complex numbers using at least one N-bit signed complex multiplier, wherein N is an integer.
Dependencies are inferred from the claim text.