Linear device value estimating method, capacitance detection method, integrated circuit, touch sensor system, and electronic device

A method of detecting capacitance, to detect a distribution of capacitance of a plurality of capacitors that are each formed on intersections of a plurality of first signal lines with a plurality of second signal lines,

• the method comprising the steps of:
• driving, in drive sections, the first signal lines in a first timing, to output from the second signal lines to the estimation sections electric charges that correspond to the capacitors, wherein the first signal lines are connected to the drive sections and the second signal lines are connected to estimation sections;
• controlling, with use of a multiplexer, in a second timing subsequent to the first timing, a switching of connections of the first signal lines with that of the second signal lines so that the first signal lines are connected to the estimation sections and the second signal lines are connected to the drive sections;
• and
• driving, in the drive sections, the second signal lines in a third timing subsequent to the second timing, to output from the first signal lines to the estimation sections the electric charges that correspond to the capacitors,
• the step of driving the first signal lines comprising:
• (A) (a) driving, on a basis of code sequences di which include elements each being either +1 or −1, the plurality of first signal lines in parallel, so that a voltage +V is applied for an element of +1 in the code sequences and that a voltage −V is applied for an element of −1 in the code sequences, and thus (b) outputting, along each of the plurality of second signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of second signal lines;
• and
• (B) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective second signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that second signal line, for each of the plurality of second signal lines, and
• the step of driving the second signal lines comprising:
• (C) (a) driving, on a basis of the code sequences, the plurality of second signal lines in parallel, so that a voltage +V is applied for the element of +1 in the code sequences and that a voltage −V is applied for the element of −1 in the code sequences, and thus (b) outputting, along each of the plurality of first signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of first signal lines;
• and
• (D) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective first signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that first signal line, for each of the plurality of first signal lines.

A method of detecting capacitance, to detect a distribution of capacitance of a plurality of capacitors that are each formed on intersections of a plurality of first signal lines with a plurality of second signal lines,

• the method comprising the steps of:
• driving, in drive sections, the first signal lines in a first timing, to output from the second signal lines to the estimation sections electric charges that correspond to the capacitors, wherein the first signal lines are connected to the drive sections and the second signal lines are connected to estimation sections;
• controlling, with use of a multiplexer, in a second timing subsequent to the first timing, a switching of connections of the first signal lines with that of the second signal lines;
• and
• driving, in the drive sections, the second signal lines in a third timing subsequent to the second timing, to output from the first signal lines to the estimation sections the electric charges that correspond to the capacitors,
• the step of driving the first signal lines comprising:
• (A) (a) driving, on a basis of code sequences di which include elements each being either +1 or −1, the plurality of first signal lines in parallel, and thus (b) outputting, to analog integrators of the estimation sections, along each of the plurality of second signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of second signal lines;
• and
• (B) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective second signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that second signal line, for each of the plurality of second signal lines, and
• the step of driving the second signal lines comprising:
• (C) (a) driving, on a basis of the code sequences, the plurality of second signal lines in parallel, and thus (b) outputting, to the analog integrator, along each of the plurality of first signal lines, a linear sum of the electric charges stored in the capacitors corresponding to that respective one of the plurality of first signal lines;
• and
• (D) estimating, on a basis of an inner product operation of (i) the linear sum of the electric charges outputted along the respective first signal line and (ii) the code sequences di, a capacitance of the capacitors formed along that first signal line, for each of the plurality of first signal lines,
• the step (A), for an element of +1 in the code sequences, driving the plurality of first signal lines at (i) a first voltage when the analog integrator is reset and (ii) a second voltage when the linear sums of the electric charges outputted along the respective second signal lines are sampled and, for an element of −1 in the code sequences, driving the plurality of first signal lines at (i) the second voltage when the analog integrator is reset and (ii) the first voltage when the linear sums are sampled.