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AssigneesUniversidad de Santiago de Compostela, Consejo Superior de Investigaciones Cientificas, Universidad de Sevilla
InventorsManuel Suárez Cambre, Víctor Manuel Brea Sánchez, Fernando Rafael Pardo Seco, Ángel Rodríguez Vázquez, Ricardo Carmona Galán
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Disclose embodiments include an image processor for feature detection comprising a single non-planar chip containing a plurality of integrated sensing and processing resources across two or more layers adapted to capture image frames and extract image features. In a particular embodiment, the non-planar chip is a three dimensional CMOS integrated circuit (3D CMOS IC) with vertical distribution of sensing and processing resources across two or more vertical integrated circuit layers. The 3D CMOS IC implements two or more feature detectors in a single chip by reusing a plurality of circuits employed for gradient and keypoint detection. Feature detectors include a scale invariant feature transform detector (SIFT), a Harris-based feature detector, and a Hessian-based feature detector.
An image processor for feature detection comprising a single non-planar chip containing a plurality of integrated sensing and processing resources across two or more layers adapted to capture image frames and extract image features, wherein said non-planar chip is a three dimensional CMOS integrated circuit with vertical distribution of sensing and processing resources across two or more vertical integrated circuit layers and wherein said three dimensional CMOS integrated circuit comprises an array of in-pixel processors and a plurality of circuits that in parallel realize a scale invariant feature transform detector (SIFT), a Harris-based feature detector, and a Hessian-based feature detector.
A method for achieving efficient image feature detection on an integrated circuit, comprising:
Dependencies are inferred from the claim text.