Parallel replica CDR to correct offset and gain in a baud rate sampling phase detector

A method for setting up a clock and data recovery circuit, the method comprising:

• recovering a clock signal and data from an analog signal in a first clock and data recovery circuit, wherein the first clock and data recovery circuit has a first phase detector with at least one of an adjustable offset or an adjustable gain;
• recovering the clock signal and the data from the analog signal in a second clock and data recovery circuit, wherein the second clock and data recovery circuit has a second phase detector with at least one of an adjustable offset or an adjustable gain;
• providing recovered data from the first clock and data recovery circuit to one or more circuits that use the recovered data;
• adaptively adjusting at least one of the adjustable offset or the adjustable gain of the second clock and data recovery circuit to generate at least one of an adjustable offset setting or an adjustable gain setting;
• applying the at least one of the adjustable offset setting or the adjustable gain setting obtained from adaptive adjustment of the second clock and data recovery circuit to the first clock and data recovery circuit;
• determining a vertical eye opening for analysis of the at least one of the adjustable offset setting or the adjustable gain setting;
• and
• selecting the at least one of the adjustable offset setting or the adjustable gain setting based at least partly on the vertical eye opening amount reaching a threshold.

An apparatus for setting up a clock and data recovery circuit, the apparatus comprising:

• a first clock and data recovery circuit having an input and an output, wherein the input is coupled to an input node, wherein the first clock and data recovery circuit has a first phase detector with at least one of an adjustable offset or an adjustable gain;
• a second clock and data recovery circuit having an input and an output, wherein the input is coupled to the input node, wherein the second clock and data recovery circuit has a second phase detector with at least one of an adjustable offset or an adjustable gain;
• a means for providing recovered data from the first clock and data recovery circuit to one or more circuits that use the recovered data;
• a means for adaptively adjusting at least one of the one or more configurable characteristics of the second clock and data recovery circuit;
• a means for applying the at least one of the adjustable offset setting or the adjustable gain setting obtained from adaptive adjustment of the second clock and data recovery circuit to the first clock and data recovery circuit;
• a means for determining a vertical eye opening for analysis of the at least one of the adjustable offset setting or the adjustable gain setting;
• and
• a means for selecting the at least one of the adjustable offset setting or the adjustable gain setting based at least partly on the vertical eye opening amount reaching a threshold.