Apparatus and methods for clock alignment for high speed interfaces

An apparatus for phase aligning at least two clocks used by respective circuitry systems, the apparatus comprising:

• a first circuit configured to sample at least a phase of a first clock used by a first circuitry system;
• a delay circuit configured to selectively delay a second clock used by a second circuitry system and set one or more of a plurality of delayed timings of the second clock;
• and
• a logic circuit configured to receive the sampled phase of the first clock and to determine which one of the plurality of delayed timings matches timing of the sampled phase and to set the delay circuit with the logic circuit to a fixed delayed timing corresponding to the one of the plurality of delayed timings that matches the sampled phase;
• wherein the delay circuit comprises a tapped delay line configurable to incrementally delay the second clock based on a code input from the logic circuit;
• wherein the first circuitry system comprises a memory controller and the second circuitry system comprises a memory physical interface;
• and
• further comprising:
• determining at least one of a first delay line value for the code input corresponding to a start of a phase detector set up window, a second delay line value for the code input corresponding to an end of a hold window, and a third delay value for the code input corresponding to the difference between the first and second delay line values.

An apparatus for phase aligning at least two clocks used by respective circuitry systems, the apparatus comprising:

• a first circuit configured to sample at least a phase of a first clock used by a first circuitry system;
• a delay circuit configured to selectively delay a second clock used by a second circuitry system and set one or more of a plurality of delayed timings of the second clock;
• and
• a logic circuit configured to receive the sampled phase of the first clock and to determine which one of the plurality of delayed timings matches timing of the sampled phase and to set the delay circuit with the logic circuit to a fixed delayed timing corresponding to the one of the plurality of delayed timings that matches the sampled phase;
• and
• further comprising:
• clock division circuitry configured to divide the second clock by a predetermined value to produce to divided second clock;
• and
• selecting a period for gating input of the second clock to the delay circuit based on timing of the divided second clock.

A method for phase aligning at least two clocks used by respective circuitry systems, the method comprising:

• sampling at least a phase of a first clock used by a first circuitry system;
• selectively delaying a second clock used by a second circuitry system and setting one or more delayed timings of the second clock;
• receiving the sampled phase of the first clock in a logic circuit and determining with the logic circuit which one of the plurality of delayed timings matches timing of the sampled phase;
• and
• setting the delay circuit with the logic circuit to a fixed delayed timing corresponding to the one of the plurality of delayed timings that matches the sampled phase;
• wherein delaying the second clock with a tapped delay line configurable to incrementally delay the second clock based on a code input from the logic circuit;
• and
• wherein the code input is determined by the logic circuit based on a comparison of the phase of the sampled first clock and a phase of the delayed second clock output from the tapped delay line.

A method for phase aligning at least two clocks used by respective circuitry systems, the method comprising:

• sampling at least a phase of a first clock used by a first circuitry system;
• selectively delaying a second clock used by a second circuitry system and setting one or more delayed timings of the second clock;
• receiving the sampled phase of the first clock in a logic circuit and determining with the logic circuit which one of the plurality of delayed timings matches timing of the sampled phase;
• and
• setting the delay circuit with the logic circuit to a fixed delayed timing corresponding to the one of the plurality of delayed timings that matches the sampled phase;
• wherein delaying the second clock with a tapped delay line configurable to incrementally delay the second clock based on a code input from the logic circuit;
• wherein the first circuitry system comprises a memory controller and the second circuitry system comprises a memory physical interface;
• and
• further comprising:
• determining at least one of a first delay line value for the code input corresponding to a start of a phase detector set up window, a second delay line value for the code input corresponding to an end of a hold window, and a third delay value for the code input corresponding to the difference between the first and second delay line values.