Partial response equalizer and related method
AssigneeRambus Inc.
InventorsChintan S. Thakkar, Kun-Yung Chang, Ting Wu
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Abstract
A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.
Claims33
A multi-phase partial response receiver, comprising:
- at least two partial response circuits, each partial response circuit to sample an input signal according to a respective phase of the input signal and to generate a value based on a previously resolved symbol from the input signal;
- and
- an output circuit to receive the values from the at least two partial response circuits, to select a timing from at least two timing choices, and to output each value according to the selected timing.
A method employed in a digital receiver that receives an input signal, comprising:
- using at least two partial response circuits to sample respective data phases of the input signal, each partial response circuit generating plural conditional samples and outputting a value selected from the plural conditional samples dependent on a previously resolved datum from another one the at least two partial response circuits;
- and
- outputting each symbol according to a selected one of at least two timing choices.
A system, comprising:
- a plurality of communications channels, each communication channel conveying a sequence of data;
- and
- a receive device having a plurality of receivers, one receiver for each communications channel, each receiver including
- at least two partial response circuits, each partial response circuit to sample an input signal according to a respective phase of the input signal and to generate a value based on at least one previously resolved datum from the input signal, and
- an output circuit to receive the values from the at least two partial response circuits, and to output each value according to a selected one of at least two clock signals.
A partial response receiver, comprising:
- a first sampler to sample an input signal according to a first clock phase of a sampling clock to generate a first sample;
- a second sampler to sample the input signal according to the first clock phase to generate a second sample;
- a select circuit that selects either the first or second sample to be output as a value according to a previously generated datum;
- and
- an output circuit that receives the value output from the select circuit, that samples the value according to each of the first and second clock phase to generate respective sampled values, and that chooses one of the one of the sampled values to output.
A multi-phase partial response receiver, comprising:
- means for sampling an input signal according to a respective phase of the input signal and for generating a value for each phase in dependence upon a previously resolved datum;
- and
- means for selecting at least one of two clock signals and for sampling each value according to a selected one of the at least two clock signals.
Dependencies are inferred from the claim text.