US 8,942,280 B1Granted

Method and apparatus for timing jitter measurement

AssigneeMarvell International Ltd.

InventorsMats Oberg, Jin Xie, Bin Ni

Life of this patent

Estimating the term…

Abstract

A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.

Claims20

Dependent claims

An apparatus for measuring timing jitter, the apparatus comprising:

a converter configured to convert a signal to a digital signal;
a phase-locked loop (PLL), coupled to the converter, configured to provide a clock signal according to a frequency of the signal;
and
an interpolator bank, coupled to the converter and including m interpolators configured to over-sample the digital signal, wherein m is an over-sampling rate and m is not smaller than 2, the interpolator bank configured to generate a sample a(t) at time t as:
a
⁡
(
t
)
=
∑
j
=
k
1
k
2
⁢
⁢
[
t
-
k
1
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k
1
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1
)
]
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⁡
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X
j
where Xi denotes a sample received from an equalizer by j-th interpolator, k1=i−M, k2=i+N, k2>k1 at time i, and M and N are integers.

152 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/174,365Filed 6 Feb 2014 · continuation
Priority: 15 Aug 2007
Granted: 27 Jan 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H04L 1/205
Using signal quality detector: jitter monitoring
G01R 31/31709
Analysis of signal quality: jitter measurements; Jitter generators
H04B 17/364
Measuring or estimating channel quality parameters: delay profiles
H04L
Digital communication

Family

Application60/955,938Us provisional application · filed 15 Aug 2007
Application12/192,877Parent of this continuation · filed 15 Aug 2008
US 8,660,171 B1Parent of this continuation
US 8,942,280 B1This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

Facts

Application

14/174,365Filed 6 Feb 2014 · continuation

Priority

15 Aug 2007

Granted

27 Jan 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H04L 1/205
Using signal quality detector: jitter monitoring
G01R 31/31709
Analysis of signal quality: jitter measurements; Jitter generators
H04B 17/364
Measuring or estimating channel quality parameters: delay profiles
H04L
Digital communication