Shared control logic for multiple queues

An integrated circuit (IC) for managing a communication path carrying multiple channels, each channel including a first-in first-out (FIFO) queue, the IC comprising:

• a buffer that delays arriving data in the communication path for an amount of time to produce delayed data such that the FIFO queue of each channel has respective arrival data and departure data aligned in channel synchronism, the amount of time being equal to a difference between a start of a cycle for the communication path receiving data in the particular channel and a start of a cycle for the communication path transmitting data in the particular channel, the amount of time at least one clock cycle for the particular channel the data remaining as serial data, excluding parallel writing or parallel reading of the data, throughout the buffer;
• channel control memory for storing FIFO control and status data for all FIFO queues;
• and
• a FIFO logic module that includes FIFO registers, wherein the FIFO registers are loaded with FIFO control and status data for a single FIFO queue, wherein the single FIFO queue is associated with a channel of the produced delayed data, and wherein read and write requests for the single FIFO queue are processed contemporaneously using the FIFO registers.

An integrated circuit (IC) comprising:

• a buffer that delays arriving data in a communication path for an amount of time to produce delayed data, the amount of time being equal to a difference between a start of a cycle for the communication path receiving data in a particular channel and a start of a cycle for the communication path transmitting data in the particular channel, wherein the amount of time is one or more clock cycles for the particular channel, the buffer configured to delay the data in serial form, with neither parallel writing of the data nor parallel reading of the data, for the one or more clock cycles;
• one FIFO data buffer per channel, the delayed data being written to the FIFO data buffer that corresponds to the channel associated with the delayed data so that the delayed data is aligned to departure data of the FIFO data buffer in channel synchronism;
• channel control memory for storing FIFO control and status data for all FIFO queues;
• and
• read and write FIFO control registers that are loaded with FIFO control and status data for the FIFO queue that corresponds to the channel associated with the delayed data, wherein read requests are processed contemporaneously with write requests for a same channel.