Multi-stage switching topology
AssigneeGoogle Inc.
InventorsDavid Fermor, Junlan Zhou
Life of this patent
Estimating the term…
Abstract
A multi-stage switching fabric provides a first tier and a second tier. The first tier may include a first plurality of switches, and the second tier may include a second plurality of switches, wherein each of the switches in the first tier are coupled to the switches in the second tier. Each of the switches in the first and second tiers may include a plurality of switching chips, wherein a given switching chip in a given switch is coupled to each other switching chip in the given switch. The fabric may further include a third tier comprising one or more core switches, wherein each switch in the second tier is coupled to at least one of the core switches.
Claims21
A switching fabric, comprising:
- a first tier comprising a first plurality of switches;
- a second tier comprising a second plurality of switches, wherein the switches in the first tier are coupled to the switches in the second tier via one or more links;
- a third tier comprising one or more core switches, wherein each switch in the second tier is coupled to at least one of the core switches via one or more links;
- wherein each switch of the first plurality of switches and second plurality of switches comprises a plurality of switching chips, each of the plurality of switching chips being coupled via intra-switch links to each other switching chip in the switch;
- and
- wherein each of the switching chips in the first tier is further coupled to a host device via a bundle of links.
A switch, comprising:
- a plurality of switching chips;
- and
- a plurality of intra-switch link bundles, the plurality of intra-switch link bundles coupling each of the plurality of switching chips to each of the other of the plurality of switching chips.
A network fabric, comprising:
- a superblock, the superblock comprising:
- a first tier comprising a plurality of switching chips, the switching chips being linked to host devices via one or more links;
- and
- a second tier comprising a plurality of arrays, each of the plurality of arrays comprising a predetermined number of switching chips, wherein at least one first switching chip in each array is linked to each other switching chip in the same array via one or more links;
- wherein each of the plurality of switching chips in the first tier is linked to the at least one first switching chip in each array;
- and
- wherein the at least one first switching chip in each array is linked to a device in a third tier.
A method of routing data within a network fabric comprising at least one switch, wherein the at least one switch comprises a first plurality of switching chips, each switching chip being linked via intra-switch links to each other switching chip in the switch, and at least one processor adapted to control the plurality of switching chips, the method comprising:
- receiving data traffic at a first switching chip;
- distributing the data traffic among each of the other switching chips in the first plurality of switching chips;
- transmitting the traffic to a block, the block comprising a second plurality of switching chips arranged in a higher network tier with respect to the at least one switch;
- determining whether the traffic destination is linked to one of the second plurality of switching chips through a second lower tier switch;
- transmitting the traffic to the second lower tier switch if the traffic destination is so linked;
- and
- transmitting the traffic to a device in hierarchy higher network tier if the traffic destination is not so linked.
Dependencies are inferred from the claim text.