Systems, memories, and methods for operating memory arrays
AssigneeMicron Technology, Inc.
InventorsVictor Wong, William F. Jones, Seth A. Eichmeyer
Life of this patent
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Abstract
Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.
Claims28
A memory, comprising:
- a memory array;
- replacement elements for replacing memory cells of the memory array;
- and
- control logic configured to control refresh of at least one replacement element in a manner of refresh that is different than a replacement solution for the memory array, wherein the manner of refresh of the at least one replacement element is dependent upon refreshing at least substantially simultaneously with a specific section of a core array.
A memory, comprising:
- a memory array;
- replacement elements for replacing memory cells of the memory array;
- and
- control logic configured to control refresh of at least one replacement element in a manner of refresh that is different than a replacement solution for the memory array, wherein the manner of refresh of the at least one replacement element includes the control logic being configured to link the at least one replacement element to refresh at substantially the same time as a specific non-neighboring section.
A memory, comprising:
- a memory array;
- replacement elements for replacing memory cells of the memory array;
- and
- control logic configured to control refresh of at least one replacement element in a manner of refresh that is different than a replacement solution for the memory array, wherein the manner of refresh of the at least one replacement element includes the control logic being configured to decode a memory address to refresh another address during a refresh operation.
A memory, comprising:
- a memory array;
- replacement elements for replacing memory cells of the memory array, wherein:
- primary memory cells are arranged in a core array of the memory array;
- replacement memory cells arranged in a replacement array, wherein the replacement array includes replacement elements located both in an edge array section and distributed throughout the sections of the core array;
- and
- control logic configured to control refresh of at least one replacement element in a manner of refresh that is different than a replacement solution for the memory array.
A method for operating a memory array, the method comprising:
- replacing at least one memory cell from a memory array with at least one replacement element according to a replacement solution;
- and
- refreshing the at least one replacement element according to a refresh solution that is different from the replacement solution by causing the at least one replacement element to be refreshed in a manner that is dependent upon refreshing a specific section of a core array.
A method for operating a memory array, the method comprising:
- replacing at least one memory cell from a memory array with at least one replacement element according to a replacement solution;
- and
- refreshing the at least one replacement element according to a refresh solution that is different from the replacement solution, wherein refreshing the at least one replacement element includes refreshing the at least one replacement element along with a plurality of sections from a plurality of sub-arrays.
Dependencies are inferred from the claim text.