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US 8,942,052 B2Granted
Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages
AssigneeInternational Business Machines Corporation
InventorsWilliam V. Huott, Michael Kugel, Juergen Pille, Rolf Sautter, Dieter Wendel
Life of this patent
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Abstract
A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET.
Claims24
A voltage selection circuit, comprising:
- cross-coupled circuitry, wherein the cross-coupled circuitry comprises a first positive-channel field effect transistor (PFET) and a second PFET, wherein:
- a source of the first PFET is coupled to a first voltage,
- a gate of the first PFET is coupled to a second voltage,
- a drain of the first PFET is coupled to an input of a header circuitry,
- wherein the header device precharges a bit line of a memory cell,
- a source of the second PFET is coupled to the second voltage,
- a gate of the second PFET is coupled to the first voltage, and
- a drain of the second PFET is coupled to the input to the header circuitry;
- and
- diode circuitry, wherein the diode circuitry comprises a third PFET and a fourth PFET, wherein:
- a source of the third PFET is coupled to the first voltage,
- a gate of the third PFET is coupled to the input to the header circuitry,
- a drain of the third PFET is coupled to the input to the header circuitry,
- a source of the fourth PFET is coupled to the second voltage,
- a gate of the fourth PFET is coupled to the input to the header circuitry, and
- a drain of the fourth PFET is coupled to the input to the header circuitry.
13 more elements
A memory comprising:
- a set of memory cells;
- a voltage selection circuit coupled to the set of memory cells, wherein the voltage selection circuit comprises:
- cross-coupled circuitry, wherein the cross-coupled circuitry comprises a first positive-channel field effect transistor (PFET) and a second PFET, wherein:
- a source of the first PFET is coupled to a first voltage,
- a gate of the first PFET is coupled to a second voltage,
- a drain of the first PFET is coupled to an input of a header circuitry,
- wherein the header device precharges a bit line of the set of memory cells,
- a source of the second PFET is coupled to the second voltage,
- a gate of the second PFET is coupled to the first voltage, and
- a drain of the second PFET is coupled to the input to the header circuitry;
- and
- diode circuitry, wherein the diode circuitry comprises a third PFET and a fourth PFET, wherein:
- a source of the third PFET is coupled to the first voltage,
- a gate of the third PFET is coupled to the input to the header circuitry,
- a drain of the third PFET is coupled to the input to the header circuitry,
- a source of the fourth PFET is coupled to the second voltage,
- a gate of the fourth PFET is coupled to the input to the header circuitry, and
- a drain of the fourth PFET is coupled to the input to the header circuitry.
15 more elements
An apparatus, comprising:
- a processor;
- and
- a memory coupled to the processor, wherein the memory comprises:
- a set of memory cells;
- a voltage selection circuit coupled to the set of memory cells, wherein the voltage selection circuit comprises:
- cross-coupled circuitry, wherein the cross-coupled circuitry comprises a first positive-channel field effect transistor (PFET) and a second PFET, wherein:
- a source of the first PFET is coupled to a first voltage,
- a gate of the first PFET is coupled to a second voltage,
- a drain of the first PFET is coupled to an input of a header circuitry, wherein the header device precharges a bit line of a memory cell,
- a source of the second PFET is coupled to the second voltage,
- a gate of the second PFET is coupled to the first voltage, and
- a drain of the second PFET is coupled to the input to the header circuitry;
- and
- diode circuitry, wherein the diode circuitry comprises a third PFET and a fourth PFET, wherein:
- a source of the third PFET is coupled to the first voltage,
- a gate of the third PFET is coupled to the input to the header circuitry,
- a drain of the third PFET is coupled to the input to the header circuitry,
- a source of the fourth PFET is coupled to the second voltage,
- a gate of the fourth PFET is coupled to the input to the header circuitry, and
- a drain of the fourth PFET is coupled to the input to the header circuitry.
17 more elements
Dependencies are inferred from the claim text.