Method of inspecting variable resistance nonvolatile memory device and variable resistance nonvolatile memory device

A variable resistance nonvolatile memory device comprising:

• a plurality of word lines arranged in parallel to each other in a first plane;
• a plurality of bit lines that are arranged in parallel to each other in a second plane parallel to the first plane, and three-dimensionally cross the word lines;
• a memory cell array having a plurality of memory cells each including a variable resistance element and a current steering element that are connected in series, each of the memory cells being located at a three-dimensional cross point of one of the word lines and one of the bit lines, the variable resistance element changing at least between a low resistance state and a high resistance state, and the current steering element carrying a current from which the current steering element is assumed to be conducting as a result of an application of a voltage exceeding a predetermined threshold voltage;
• a memory cell selection circuit that selects one of the memory cells by selecting at least one of the word lines and at least one of the bit lines;
• and
• a read circuit that reads a resistance state of the selected memory cell,
• wherein the read circuit includes:
• a bit-line control voltage generation circuit that (i) generates a first voltage higher than the threshold voltage and a second voltage lower than the threshold voltage and (ii) outputs the first voltage and the second voltage from a first output terminal and a second output terminal, respectively;
• a bit-line voltage switching circuit that is connected to the bit-line control voltage generation circuit and switches between the first voltage and the second voltage to provide a corresponding one of the first voltage and the second voltage;
• a bit-line voltage steering circuit that has (i) an output terminal connected to the memory cell selection circuit and (ii) a control terminal connected to the bit-line voltage switching circuit;
• and
• a detection circuit that detects a current passing through the selected memory cell via the selected word line and the selected bit line as a result of an application of a voltage to the selected bit line, the voltage being determined according to a voltage to be applied to the control terminal of the bit-line voltage steering circuit,
• wherein, when the resistance state of the memory cell is read by the application of the first voltage, the detection circuit provides (i) a first logic output when the selected memory cell is in the low resistance state and (ii) a second logic output when the selected memory cell is in the high resistance state, and
• when the resistance state of the memory cell is read by the application of the second voltage and the current steering element of the selected memory cell has a short-circuit fault, the detection circuit provides (i) the first logic output when the variable resistance element is in the low resistance state, and (ii) one of the first logic output and the second logic output when the variable resistance element is in the high resistance state.