Channel hot carrier tolerant tracking circuit for signal development on a memory SRAM
AssigneeTexas Instruments Incorporated
InventorSrinivasa Sridhara
Life of this patent
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Abstract
An embodiment of the invention discloses an electronic device for reducing degradation in NMOS circuits in a tracking circuit. A first multiplexer selects, based on N bits from a row address in a memory array, which tracking circuit from a group of 2N tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal. A second multiplexer selects, based on the N bits from the row address for a memory array, which output from the tracking circuits is used to enable the sense amp enable signal.
Claims11
An electronic device for reducing transistor degradation of NMOS transistors in a delay line comprising:
- a first multiplexer having a data input, N control inputs and 2N outputs wherein the data input is connected to a dummy word line signal, wherein the 2N outputs are electrically connected to an input of 2N delay line circuits respectively;
- wherein the N control inputs are electrically connected to a control signal that represents the logical states of N bits selected from a row address of an SRAM array;
- a second multiplexer having a 2N data inputs, N control inputs and an output, wherein the 2N data inputs are electrically connected to 2N output from the 2N delay lines respectively;
- wherein the N control inputs are electrically connected to the control signal that represents the logical state of N bits selected from a row address of an SRAM array;
- wherein the output of the second multiplexer is used to enable sense amps in the SRAM array.
An electronic device for reducing transistor degradation of NMOS transistors in a dummy word line circuit comprising:
- a first multiplexer having a data input, N control inputs and 2N outputs wherein the data input is connected to a dummy word line signal, wherein the 2N outputs are electrically connected to a dummy word line from 2N dummy word line circuits respectively;
- wherein the N control inputs are electrically connected to a control signal that represents the logical states of N bits selected from a row address of an SRAM array;
- a buffer having an output and an input wherein the input of the buffer is electrically connected to a first bit line of a bit line pair wherein the bit line pair is connected to a dummy bit cell from each of the 2N dummy word line circuit;
- and wherein the output of the buffer is used to enable sense amps in the SRAM array.
An electronic device for reducing transistor degradation of NMOS transistors in dummy word line circuits comprising:
- a first multiplexer having a data input, 1 control input and 2 outputs wherein the data input is connected to a dummy word line signal, wherein the 2 outputs are electrically connected to a first dummy word line circuit and a second dummy work line circuit respectively;
- wherein the control input is electrically connected to a control signal that represents the logical state of the least significant bit selected from a row address of an SRAM array;
- M second multiplexers wherein each multiplexer in the M second multiplexers has two inputs, two outputs and a control signal;
- wherein the inputs to each multiplexer is electrically connected to M bit line pairs of the dummy memory cells in the first and second dummy word line circuits respectively;
- wherein the two outputs of each multiplexer in the M−1 second multiplexers are electrically connected to the bit line pairs connected to the first dummy memory cells in the first and second dummy word line circuits;
- and
- a logic block having a multi-bit input and M outputs;
- where a multi-bit control signal is electrically connected to the multi-bit input;
- wherein each of the M outputs of the logic block is electrically connected to the control signal of each of the M second multiplexer respectively;
- wherein the multi-bit control signal determines how may outputs from the M second multiplexers are electrically connected to bit line pairs connected to the first dummy memory cells in the first and second dummy word line circuits.
Dependencies are inferred from the claim text.