Memory apparatus and methods

A memory device comprising:

• a string of memory cells, the memory cells located on different levels of the memory device;
• a data line;
• and
• a transistor including a gate configured to be coupled to at least one of a first potential and a second potential during a memory operation if a memory cell of the string of the memory cells is selected to provide information stored in the memory cell to the data line, and the gate configured to be decoupled from the first potential and the second potential if no memory cell in the string of memory cells is selected to provide information stored in a memory cell in the string of memory cells to the data line during the memory operation and if at least one additional memory cell in an additional string of memory cells is selected to provide information stored in the additional memory cell to the data line during the memory operation.

A memory device comprising:

• a first block of memory cells and a second block of memory cells, the memory cells are cells located on different levels of the memory device;
• a line to exchange information with the first and second blocks of memory cells;
• a first transistor coupled between the line and the first block of memory cells;
• a second transistor coupled between the line and the second block of memory cells;
• and
• a module configured to access at least one memory cell of the first block of memory cells in a memory operation and to access no memory cells of the second block of memory cells in the memory operation, the module configured to couple a gate of the first transistor and a gate of the second transistor to a reference potential during a first time interval of the memory operation, and to couple the gate of the first transistor to a first voltage during a second time interval of the memory operation, and the module configured to decouple the gate of the second transistor from the reference potential during the second time interval of the memory operation.

A method comprising:

• coupling a gate of a transistor to a first node during a first time interval of a memory operation of a device such that a string of memory cells is decoupled from a data line during the first time interval if at least one memory cell of the string of the memory cells is selected to be accessed during the memory operation, the memory cells located on different levels of the device;
• coupling the gate of the transistor to a second node during a second time interval of the memory operation such that the string of memory cells is coupled to the data line through the transistor during the second time interval if at least one memory cell of string of the memory cells is selected to be accessed during the memory operation;
• and
• decoupling the gate of the transistor from the first and second nodes if no memory cell in the string of memory cells is selected to be accessed during the memory operation and if at least one memory cell of an additional string of memory cells associated with the data line is selected to be accessed.