Non-volatile storage with process that reduces read disturb on end wordlines

A non-volatile storage system, comprising:

• a plurality of NAND strings, each NAND string includes multiple data memory cells;
• a plurality of word lines connected to the NAND strings;
• and
• one or more managing circuits connected to the word lines and in communication with the data memory cells via the word lines to program and read the data memory cells, the one or more managing circuits are configured to program data memory cells at a first end of the NAND strings by applying to a first end word line a set of program pulses that initially increase in magnitude between pulses by a first step size, the one or more managing circuits are configured to program additional data memory cells of the NAND strings by applying to middle word lines a set of program pulses that initially increase in magnitude between pulses by a second step size, the second step size is greater than the first step size, the one or more managing circuits are configured to apply a read compare voltage to a selected word line that is connected to selected data memory cells of the additional data memory cells subsequent to the programming of the additional data memory cells of the NAND strings, the one or more managing circuits are configured to apply a first read pass voltage to the first end word line while applying the read compare voltage to the selected word line, the one or more managing circuits are configured to apply a set of one or more read pass voltages to the middle word lines while applying the read compare voltage to the selected word line, the set of one or more read pass voltages are all higher voltages than the first read pass voltage, the one or more managing circuits are configured to sense the selected data memory cells in response to the read compare voltage.

A method of operating non-volatile storage, comprising:

• programming data memory cells at a first end of a set of NAND strings by applying to a first end word line a set of program pulses that increase in magnitude between pulses by a first step size;
• programming additional data memory cells of the NAND strings by applying to middle word lines a set of program pulses that increase in magnitude between pulses by a second step size, the second step size is greater than the first step size, the data memory cells at the first end of the set of NAND strings are being programmed to the same data states as the additional data memory cells;
• subsequent to the programming of the data memory cells at the first end of the NAND strings and the programming of the additional data memory cells of the NAND strings, applying a read compare voltage to a selected word line that is connected to selected data memory cells of the additional data memory cells;
• applying a first read pass voltage to the first end word line while applying the read compare voltage to the selected word line;
• applying a set of one or more read pass voltages to the middle word lines while applying the read compare voltage to the selected word line, the set of one or more read pass voltages are all higher voltages than the first read pass voltage;
• and
• sensing the selected data memory cells in response to the read compare voltage.

A method of operating non-volatile storage, comprising:

• programming a data memory cell at a first end of a NAND string using a set of program pulses that increase in magnitude between pulses by a first step size, including choosing to use the first step size based on position of the data memory cell at the first end of the NAND string;
• programming additional data memory cells of the NAND string using a set of program pulses that increase in magnitude between pulses by a second step size, the second step size is greater than the first step size;
• subsequent to the programming of the data memory cell at the first end of the NAND string and the programming of the additional data memory cells of the NAND string, applying a read compare voltage to the data memory cell at the first end of a NAND string;
• applying a set of one or more read pass voltages to multiple unselected data memory cells of the NAND string while applying the read compare voltage to the data memory cell at the first end of the NAND string;
• applying a first read pass voltage to a dummy memory cell that is adjacent to the data memory cell at the first end of the NAND string while applying the read compare voltage to the data memory cell at the first end of the NAND string and while the applying of the one or more read pass voltages to the multiple unselected data memory cells, the first read pass voltage is greater than all of the one or more read pass voltages;
• and
• sensing a condition of the data memory cell at the first end of the NAND string in response to the read compare voltage.

A non-volatile storage system, comprising:

• a NAND string that includes multiple data memory cells and at least one dummy memory cell;
• a plurality of word lines connected to the memory cells;
• and
• one or more managing circuits connected to the word lines and in communication with the data memory cells via the word lines to program and read the data memory cells, the one or more managing circuits are configured to program a data memory cell at a first end of a NAND string using a set of program pulses that increase in magnitude between pulses by a first step size such that the first step size is chosen based on position of the data memory cell at the first end of the NAND string, the one or more managing circuits are configured to program additional data memory cells of the NAND string using a set of program pulses that increase in magnitude between pulses by a second step size, the second step size is greater than the first step size, the one or more managing circuits are configured to apply a read compare voltage to the data memory cell at the first end of a NAND string subsequent to the programming of the data memory cell at the first end of the NAND string and the programming of the additional data memory cells of the NAND string, the one or more managing circuits are configured to apply a set of one or more read pass voltages to multiple unselected data memory cells of the NAND string while applying the read compare voltage to the data memory cell at the first end of the NAND string, the one or more managing circuits are configured to apply a first read pass voltage to a dummy memory cell that is adjacent to the data memory cell at the first end of the NAND string while applying the read compare voltage to the data memory cell at the first end of the NAND string and while applying the one or more read pass voltages to the multiple unselected data memory cells, the first read pass voltage is greater than all of the one or more read pass voltages, the one or more managing circuits are configured to sense a condition of the data memory cell at the first end of the NAND string in response to the read compare voltage.