Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells

A method for controlling a memory device, comprising the steps of:

• providing a memory cell array, wherein the memory cell array comprises a plurality of even local bit lines and a plurality of odd local bit lines;
• providing a column decoder, wherein the column decoder comprises a plurality of even pass transistors, a plurality of even clamp transistors, a plurality of odd pass transistors, and a plurality of odd clamp transistors, wherein the even pass transistors are configured to selectively couple the even local bit lines to a global bit line, the even clamp transistors are configured to selectively couple the even local bit lines to a ground voltage, the odd pass transistors are configured to selectively couple the odd local bit lines to the global bit line, and the odd clamp transistors are configured to selectively couple the odd local bit lines to the ground voltage;
• selecting and enabling one of the even pass transistors or one of the odd pass transistors;
• when one of the even pass transistors is selected and enabled, disabling all of the even clamp transistors, and enabling all of the odd clamp transistors to pull down all of the odd local bit lines to the ground voltage;
• and
• when one of the odd pass transistors is selected and enabled, disabling all of the odd clamp transistors, and enabling all of the even clamp transistors to pull down all of the even local bit lines to the ground voltage.