Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device, comprising:

• a memory cell array configured having a plurality of blocks arranged therein, each of the blocks configured as an arrangement of NAND cell units, each of the NAND cell units configured having a plurality of electrically rewriteable memory cells and a select transistor connected in series;
• and
• a row decoder configured to select any one of the blocks of the memory cell array and supply to any one of said blocks a voltage required in various kinds of operations,
• the row decoder comprising:
• a first sub row decoder disposed on a first side of the memory cell array;
• and a second sub row decoder disposed on a second side which is an opposite side to the first side of the memory cell array,
• the first sub row decoder comprising:
• a first gate circuit including a plurality of first transfer transistors disposed in a first region and connected to first ones of the memory cells, and plurality of second transfer transistors disposed in a second region and connected to respective ones of the select transistors, the second region being a residual region of the first region;
• and a boost circuit for generating a control signal supplied to a gate of the first transfer transistors and the second transfer transistors, and
• the second sub row decoder comprising a second gate circuit that includes fifth transfer transistors disposed in a third the first region and connected to second ones of the memory cells, and sixth transfer transistors disposed in a fourth region and connected to respective ones of the select transistors, the fourth region being a residual region of the third region, and the fifth transfer transistors and the sixth transfer transistors being supplied with the control signal from the boost circuit in the first row decoder.