Non-sequential encoding scheme for multi-level cell (MLC) memory cells
AssigneeSeagate Technology LLC
InventorsYiran Chen, Dadi Setiadi, Patrick J. Ryan
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Abstract
Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.
Claims20
A method comprising:
- selecting a non-sequential encoding scheme that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected multi-level cell (MLC) memory cell in relation to write effort associated with each of said plurality of physical states, the selected encoding scheme assigning a first multi-bit logical value to a first physical state having a first value, a second multi-bit logical value to a second physical state having a second value, and a third multi-bit logical value to a third physical state having a third value between the first value and the second value, the third multi-bit logical value greater than the first and second multi-bit logical values;
- and
- writing data to the selected MLC memory cell in relation to said non-sequential encoding scheme.
A method comprising:
- providing an array of multi-level cell (MLC) memory cells, each cell adapted to store a plural number n independent bits in relation to 2n physical states of the cell;
- assigning a non-sequential encoding scheme to the array that associates each physical state of a selected cell to a different n-bit combination of logical bit values in relation to a write effort required to achieve said physical state by storing data to the array in accordance with a predetermined sequence of write commands and associated write data arranged as multi-bit logical values, accumulating frequency statistics for each multi-bit logical value written to said array during the storing data step, storing said frequency statistics in a memory, and using the stored frequency statistics to identify the assigned non-sequential encoding scheme;
- and
- writing a selected n-bit combination of logical bit values to the selected cell using the assigned encoding scheme.
An apparatus comprising:
- an array of multi-level cell (MLC) memory cells, each cell adapted to store a plural number n independent bits in relation to 2n physical states of the cell;
- a controller adapted to assign a non-sequential encoding scheme to the array that associates each physical state of a selected cell to a different multi-bit logical value in relation to a write effort required to achieve said physical state, and to subsequently direct a write operation upon the array to write a selected multi-bit logical value to the selected cell using the assigned encoding scheme;
- and
- a memory which stores a conversion table that associates each of the physical states with its associated multi-bit logical value, wherein the controller utilizes the conversion table during write and read operations with the array.
Dependencies are inferred from the claim text.