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US 8,942,034 B2Granted
System and method of programming a memory cell
AssigneeQUALCOMM Incorporated
InventorsXia Li, Bin Yang
Life of this patent
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Abstract
A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.
Claims45
An apparatus comprising:
- a semiconductor transistor structure including a source overlap region and a drain overlap region, wherein the source overlap region is selectively biasable to create a first breakdown condition between the source overlap region and a gate of the semiconductor transistor structure, and wherein the drain overlap region is selectively biasable to create a second breakdown condition between the drain overlap region and the gate;
- a first access transistor coupled to the semiconductor transistor structure;
- a second access transistor coupled to the semiconductor transistor structure;
- and
- a well line coupled to a body of the first access transistor and coupled to a body of the second access transistor.
2 more elements
A method comprising:
- applying a voltage to a well line that is coupled to a body of a first access transistor and that is coupled to a body of a second access transistor, the first access transistor and the second access transistor coupled to a semiconductor transistor structure;
- and
- selectively creating a first breakdown condition and a second breakdown condition at the semiconductor transistor structure, wherein the first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure, and wherein the second breakdown condition is between a drain overlap region of the semiconductor transistor structure and the gate.
An apparatus comprising:
- means for creating a first breakdown condition between a source overlap region of a semiconductor transistor structure and a gate of the semiconductor transistor structure;
- means for creating a second breakdown condition between a drain overlap region of the semiconductor transistor structure and the gate;
- first means for accessing the semiconductor transistor structure;
- second means for accessing the semiconductor structure;
- and
- means for biasing a body contact of the semiconductor transistor structure, wherein the means for biasing the body contact of the semiconductor transistor structure is coupled to a body of the first means and coupled to a body of the second means.
3 more elements
A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause the processor to:
- apply a voltage to a well line that is coupled to a body of a first access transistor and that is coupled to a body of a second access transistor, the first access transistor and the second access transistor coupled to a semiconductor transistor structure;
- and
- selectively create a first breakdown condition and a second breakdown condition at the semiconductor transistor structure, wherein the first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure and wherein the second breakdown condition is between a drain overlap region of the semiconductor transistor structure and the gate.
A method comprising:
- a step for applying a voltage to a well line that is coupled to a body of a first access transistor and that is coupled to a body of a second access transistor, the first access transistor and the second access transistor coupled to a semiconductor transistor structure;
- a step for creating a first breakdown condition between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure;
- and
- a step for creating a second breakdown condition between a drain overlap region of the semiconductor transistor structure and the gate.
1 more element
A method comprising:
- receiving design information representing at least one physical property of a semiconductor device, the semiconductor device comprising:
- a semiconductor transistor structure including a source overlap region and a drain overlap region, wherein the source overlap region is selectively biasable to create a first breakdown condition between the source overlap region and a gate of the semiconductor transistor structure, and wherein the drain overlap region is selectively biasable to create a second breakdown condition between the drain overlap region and the gate;
- a first access transistor coupled to the semiconductor transistor structure;
- a second access transistor coupled to the semiconductor transistor structure;
- and
- a well line coupled to a body of the first access transistor and coupled to a body of the second access transistor;
- transforming the design information to comply with a file format;
- and
- generating a data file including the transformed design information.
6 more elements
Dependencies are inferred from the claim text.