Memory storage circuit and method of driving memory storage circuit

A method of driving a memory storage circuit, the method comprising:

• performing a store operation for storing a pair of complementary logic data with different electrical potentials to a first resistive memory element in a non-volatile memory portion and a second resistive memory element in the non-volatile memory portion as different resistance states, wherein each of the first and second resistive memory elements is a resistive random access memory (RRAM) device that includes a first electrode, a second electrode, and an oxygen getter layer between the first electrode and the second electrode, the first and second electrodes of the first resistive memory element are respectively coupled to a first node in a volatile memory portion and a second electrode of a first transistor in a control portion, and the first and second electrodes of the second resistive memory element are respectively coupled to a second node in the volatile memory portion and a second electrode of a second transistor in the control portion, the store operation including:
• a first operation for configuring a first one of the first resistive memory element and the second resistive memory element to a low resistance state based on the electrical potentials at the first node in the volatile memory portion and the second node in the volatile memory portion;
• and
• a second operation for configuring a second one of the first resistive memory element and the second resistive memory element to a high resistance state based on the electrical potentials at the first node and the second node.

A method of driving a memory storage circuit, the method comprising:

• receiving logic data at a volatile memory portion, storing the logic data in the volatile memory portion, and outputting the logic data stored in the volatile memory portion;
• determining whether a standby state is pending, and when a standby state is pending, storing the logic data stored in the volatile memory portion to a first resistive memory element and a second resistive memory element, wherein each of the first and second resistive memory elements is a resistive random access memory (RRAM) device that includes a first electrode, a second electrode, and an oxygen getter layer between the first electrode and the second electrode;
• and
• determining whether a restore operation is required, and when a restore operation is required, restoring the logic data stored in the first resistive memory element and the second resistive memory element to the volatile memory portion,
• wherein the storing the logic data stored in the volatile memory portion to the first resistive memory element and the second resistive memory element includes:
• configuring a first one of the first resistive memory element and the second resistive memory element into a low resistance state;
• and
• configuring a second one of the first resistive memory element and the second resistive memory element into a high resistance state.