Circuit arrangement and a method of writing states to a memory cell

A method of writing a first state or a second state to a memory cell wherein writing the first state to the memory cell comprises electrically connecting a first switch, the first switch in electrical connection to a first end of the memory cell, to a first voltage and electrically connecting a second switch, the second switch in electrical connection to a second end of the memory cell, to a fourth voltage to apply a first potential difference between a first and a second end of the memory cell, the first potential difference causing formation of the first state in the memory cell;

• wherein writing the second state to the memory cell comprises electrically connecting the first switch to a second voltage and electrically connecting the second switch to a third voltage to apply a second potential difference between the first and second ends of the memory cell, the second potential difference causing formation of the second state in the memory cell;
• wherein only one state is written to the memory cell at any time;
• wherein a voltage regulating circuit arrangement is in electrical connection with the first switch configured to generate the first voltage;
• and
• wherein the voltage regulating circuit arrangement comprises:
• a transistor having a controlling terminal, a first controlled terminal and a second controlled terminal, the second controlled terminal in electrical connection to the first switch, the first controlled terminal configured to be electrically connected to an unregulated voltage source;
• a differential operational amplifier having an output terminal, a first input terminal and a second input terminal, the output terminal in electrical connection to the controlling terminal of the transistor and the first input terminal is configured to be electrically connected to a reference voltage source;
• a first resistor having a first end and a second end, the first end of the first resistor in electrical connection to the second controlled terminal of the transistor and the second end of the first resistor in electrical connection to the second input terminal of the amplifier;
• a second resistor having a first end and a second end, the first end of the second resistor in electrical connection to the second end of the first resistor and the second end of the second resistor configured to be connected to ground;
• and
• a capacitor having a first end and a second end, the first end of the capacitor in electrical connection to the first end of the first resistor and the second end of the capacitor configured to be connected to ground;
• and
• wherein the voltage regulating circuit arrangement is configured such that the transistor is triggered by the differential operational amplifier to limit the first voltage generated at the second controlled terminal when the difference between the first voltage and the reference voltage source exceeds a predetermined value.

A circuit arrangement for writing a state to a memory cell comprising:

• a memory cell having a first end and a second end;
• a switching arrangement in electrical connection with the memory cell, the switching arrangement comprising a transistor;
• a presetting circuit arrangement in electrical connection to the transistor, the presetting circuit arrangement configured to trigger the transistor, the transistor of the switching arrangement upon trigger is configured to electrically connect the memory cell to a voltage source during writing the state to generate a potential difference between the first end and the second end of the memory cell, the potential difference causing formation of the state in the memory cell;
• a detection circuit configured to detect a variable associated with the formation of the state in the memory cell;
• and
• a feedback circuit arrangement in electrical connection between the detection circuit and the switching arrangement, the feedback circuit configured to trigger the switching arrangement to limit the potential difference between the first end and the second end of the memory cell upon detection by the detection circuit that the variable has a predetermined value.

A method for writing a state to a memory cell comprising:

• providing a potential difference across a first end and a second end of the memory cell to cause formation of the state;
• detecting a variable associated with the formation of the state in the memory cell;
• and
• limiting the potential difference between the first end and the second end of the memory cell upon detection that the variable has a predetermined value;
• wherein the potential difference is generated during writing the state between the first end and the second end of the memory cell by a presetting circuit arrangement in electrical connection to a transistor of a switching arrangement, the transistor upon trigger by the presetting circuit is configured to electrically connect the memory cell to a voltage source.