Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption
AssigneeRadiant Technologies, Inc.
InventorJoseph T. Evans
Life of this patent
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Abstract
A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.
Claims6
A method for operating a circuit comprising a circuit element input and a circuit element output and an AML circuit comprising a transparent latch and a transparent AML connected in series, said AML circuit having an AML circuit input connected to said circuit element output and an AML circuit output connected to said circuit element input, said method comprising:
- isolating said AML input from said circuit element output;
- connecting said AML output to said latch for a first period of time after said AML has recalled a value stored therein;
- disconnecting said AML output from said latch;
- connecting said circuit element output to said AML input;
- and
- disconnecting AML input from the circuit element output.
Dependencies are inferred from the claim text.