Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics

#The present invention relates to stacked microelectronic assemblies and methods of making such assemblies, and to components useful in such assemblies.

#Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face. In “flip chip” designs, the front face of the chip confronts the face of a package substrate, i.e., chip carrier and the contacts on the chip are bonded directly to contacts of the chip carrier by solder balls or other connecting elements. In turn, the chip carrier can be bonded to a circuit panel through terminals overlying the front face of the chip. The “flip chip” design provides a relatively compact arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip's front face, such as disclosed, for example, in certain embodiments of commonly-assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,679,977, the disclosures of which are incorporated herein by reference.

#Certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip-chip bonding. Packages which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself are commonly referred to as “chip-sized packages.”

#FIG. 1 is a diagrammatic sectional elevation view of a stacked microelectronic assembly according to an embodiment of the present invention;

#FIG. 2 is a bottom view of the stacked assembly of FIG. 1;

#FIG. 3 is a diagrammatic sectional view of a stacked microelectronic arrangement according to another embodiment of the present invention;

#With reference to FIG. 1, a stacked microelectronic assembly 10 according to an embodiment of the present invention includes a first microelectronic element 12 and a second microelectronic element 14. In some embodiments, the first and second microelectronic elements 12 and 14 may be a semiconductor chip, a wafer, or the like.

#The first microelectronic element 12 has a front surface 16, a rear surface 18 remote therefrom, and first and second edges 27, 29, extending between the front and rear surfaces. The front surface 16 of the first microelectronic element 12 includes first and second end regions 15 and 17 and a central region 13 located between the first and second end regions 15 and 17. The first end region 15 extends between the central region 13 and first edge 27, and the second end region 17 extends between the central region 13 and the second edge 29. Electrical contacts 20 are exposed at the front surface 16 of the first microelectronic element 12. As used in this disclosure, a statement that an electrically conductive element is “exposed at” a surface of a structure indicates that the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to the surface toward the surface from outside the structure. Thus, a terminal or other conductive element which is exposed at a surface of a structure may project from such surface; may be flush with such surface; or may be recessed relative to such surface and exposed through a hole or depression in the structure. The contacts 20 of the first microelectronic element 12 are exposed at the front surface 16 within the central region 13. For example, contacts 20 may be arranged in one or two parallel rows adjacent the center of first surface 16.

#The second microelectronic element 14 has a front surface 22, a rear surface 24 remote therefrom, and first and second edges 35, 37, extending between the front and rear surfaces. The front surface 22 of the second microelectronic element 14 includes first and second end regions 21 and 23 and a central region 19 located between the first and second end regions 21 and 23. The first end region 21 extends between the central region 19 and first edge 35, and the second end region 23 extends between the central region 19 and the second edge 37. Electrical contacts 26 are exposed at the front surface 22 of the second microelectronic element 14. The contacts 26 of the second microelectronic element 14 are exposed at the front surface 22 within the central region 19. For example, contacts 26 may be arranged in one or two parallel rows adjacent the center of first surface 22.